From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 7AAB53239 for ; Tue, 7 Jul 2015 12:10:35 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 07 Jul 2015 03:10:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,422,1432623600"; d="scan'208";a="724232995" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.220.92]) by orsmga001.jf.intel.com with SMTP; 07 Jul 2015 03:10:32 -0700 Received: by (sSMTP sendmail emulation); Tue, 07 Jul 2015 11:10:32 +0025 Date: Tue, 7 Jul 2015 11:10:31 +0100 From: Bruce Richardson To: Tony Lu Message-ID: <20150707101031.GA7040@bricha3-MOBL3> References: <1436172698-21749-1-git-send-email-zlu@ezchip.com> <1436172698-21749-9-git-send-email-zlu@ezchip.com> <20150706153758.GD3680@bricha3-MOBL3> <000f01d0b895$8ccbf8c0$a663ea40$@com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <000f01d0b895$8ccbf8c0$a663ea40$@com> Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on element alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jul 2015 10:10:36 -0000 On Tue, Jul 07, 2015 at 05:15:41PM +0800, Tony Lu wrote: > > > >-----Original Message----- > >From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bruce Richardson > >Sent: Monday, July 06, 2015 11:38 PM > >To: Zhigang Lu > >Cc: dev@dpdk.org > >Subject: Re: [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on > >element alignment > > > >On Mon, Jul 06, 2015 at 04:51:33PM +0800, Zhigang Lu wrote: > >> On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware > >> buffer manager require a 128-byte alignment. With this change, we > >> allow configuration based override of the element alignment, and > >> default to RTE_CACHE_LINE_SIZE if left unspecified. > >> > >> Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7 > >> Signed-off-by: Zhigang Lu > > > >This looks an OK change. However, would it be worthwhile making this a > runtime > >parameter rather than a compile-time one? Is it likely that we will ever > have a > >case where someone wants two mempools with different alignments (and > >where using the larger of the two would be problematic)? > > For now, I don't think it is very much worthwhile making this a runtime > parameter, > since doing so requires changing the mempool library API, and also the users > of mempool > do not quite care about the underlying alignments. Currently, the alignment > for mempool > objects is mostly a hardware requirement (currently RTE_CACHE_LINE_SIZE for > good > performance). And now we are defining a new RTE_MEMPOOL_ALIGN for mempool > alignment requirement for cases where someone needs other alignments than > RTE_CACHE_LINE_SIZE. > > If someone wants two mempools with different alignments, using the larger > one would > not be a problem in current mempool implementation. Because even for the > case where > there is one alignment requirement RTE_CACHE_LINE_SIZE, we would provide > larger one > (2* RTE_CACHE_LINE_SIZE and larger) for allocated mempool objects, as those > objects > are continuous in memory. So we could not avoid larger one in current > implementation. > > Thanks again for reviewing! > -Zhigang > > >/Bruce > Ok, makes sense. /Bruce