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BLUPR0701MB1713; 5:pTVkAb84bkvfOU8lypr96FUlO6FBz9LqYsZ8QbbwTj3ThBvUIIxnOc06E5Ds2s1ffe/btPBX4VpKSHaN1FfOX9EcEtKjgEtX9M1tyJJ72tPvil88fnFDedxMbizAiKpfPsOqeLuoR9uhxDeGCHnhkA==; 24:m7K2nekbLWnLx9xHjURapLay6x9GKb2N04d1Ab/pR50udRKF+6MKGdT2ZphfFDPXyjst2aMBT5gH1lMkQiPj7A0l3pWcJDHwxL2RI1dmW4g= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2015 14:44:10.5054 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1713 Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH 2/4] eal/acl: enable acl for armv7-a X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Dec 2015 14:44:15 -0000 On Tue, Dec 01, 2015 at 01:41:14PM -0500, Jianbo Liu wrote: > Implement vqtbl1q_u8 intrinsic function, which is not support in armv7-a. > > Signed-off-by: Jianbo Liu > --- > config/defconfig_arm-armv7a-linuxapp-gcc | 1 - > lib/librte_acl/Makefile | 2 +- > lib/librte_acl/rte_acl.c | 2 +- > lib/librte_eal/common/include/arch/arm/rte_vect.h | 23 +++++++++++++++++++++++ > 4 files changed, 25 insertions(+), 3 deletions(-) > > diff --git a/config/defconfig_arm-armv7a-linuxapp-gcc b/config/defconfig_arm-armv7a-linuxapp-gcc > index 9924ff9..cbebd64 100644 > --- a/config/defconfig_arm-armv7a-linuxapp-gcc > +++ b/config/defconfig_arm-armv7a-linuxapp-gcc > @@ -53,7 +53,6 @@ CONFIG_RTE_LIBRTE_KNI=n > CONFIG_RTE_EAL_IGB_UIO=n > > # fails to compile on ARM > -CONFIG_RTE_LIBRTE_ACL=n > CONFIG_RTE_LIBRTE_LPM=n > CONFIG_RTE_LIBRTE_TABLE=n > CONFIG_RTE_LIBRTE_PIPELINE=n > diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile > index 897237d..2e394c9 100644 > --- a/lib/librte_acl/Makefile > +++ b/lib/librte_acl/Makefile > @@ -49,7 +49,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_bld.c > SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_gen.c > SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c > > -ifeq ($(CONFIG_RTE_ARCH_ARM64),y) > +ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),) > SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c > CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized > else > diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c > index e2fdebd..339aace 100644 > --- a/lib/librte_acl/rte_acl.c > +++ b/lib/librte_acl/rte_acl.c > @@ -114,7 +114,7 @@ rte_acl_init(void) > { > enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT; > > -#ifdef RTE_ARCH_ARM64 > +#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64) > alg = RTE_ACL_CLASSIFY_NEON; I believe SIMD is optional in armv7. If true, select alg as RTE_ACL_CLASSIFY_NEON only when cpufeature NEON enabled. > #else > #ifdef CC_AVX2_SUPPORT > diff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h > index 21cdb4d..a33c054 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_vect.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h > @@ -53,6 +53,29 @@ typedef union rte_xmm { > double pd[XMM_SIZE / sizeof(double)]; > } __attribute__((aligned(16))) rte_xmm_t; > > +#ifdef RTE_ARCH_ARM > +/* NEON intrinsic vqtbl1q_u8() is not supported in ARMv7-A(AArch32) */ > +static __inline uint8x16_t > +vqtbl1q_u8(uint8x16_t a, uint8x16_t b) > +{ > + uint8_t i, pos; > + rte_xmm_t rte_a, rte_b, rte_ret; > + > + vst1q_u8(rte_a.u8, a); > + vst1q_u8(rte_b.u8, b); > + > + for (i = 0; i < 16; i++) { > + pos = rte_b.u8[i]; > + if (pos < 16) > + rte_ret.u8[i] = rte_a.u8[pos]; > + else > + rte_ret.u8[i] = 0; > + } > + > + return vld1q_u8(rte_ret.u8); > +} > +#endif > + > #ifdef __cplusplus > } > #endif > -- > 1.8.3.1 >