Re: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

[Bruce Richardson <bruce.richardson@intel.com>]

On Fri, Apr 15, 2016 at 03:39:09PM +0200, Tomasz Kulasek wrote:
> CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
> large_shift: In expression 1 << pool, left shifting by more than 31 bits
> has undefined behavior. The shift amount, pool, is at least 32.
> 
> This patch limits mask shift to be in range of 32 bit PFVFRE[1] register,
> for pool > 31.
> 
> Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")
> 
> Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
> ---
>  drivers/net/ixgbe/ixgbe_ethdev.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
> index 3f1ebc1..f676a64 100644
> --- a/drivers/net/ixgbe/ixgbe_ethdev.c
> +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
> @@ -4401,7 +4401,7 @@ ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
>  
>  	addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
>  	reg = IXGBE_READ_REG(hw, addr);
> -	val = bit1 << pool;
> +	val = bit1 << (pool & 0x01F);
>  
Are we sure this is the correct way to fix this. Rather than silently truncating
the pool value, are we not better to check our input parameters and return
EINVAL to the caller if pool overflows?

/Bruce