From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id D7CC02B88 for ; Thu, 6 Oct 2016 04:22:47 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 05 Oct 2016 19:22:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,451,1473145200"; d="scan'208";a="1066730490" Received: from ar11-dell-r730-02-jeff.jf.intel.com ([10.166.45.35]) by fmsmga002.fm.intel.com with ESMTP; 05 Oct 2016 19:22:46 -0700 Date: Wed, 5 Oct 2016 19:19:45 -0700 From: Jeff Shaw To: "Chen, Jing D" Cc: "Shaw, Jeffrey B" , "dev@dpdk.org" , "Zhang, Helin" , "Wu, Jingjing" , "damarion@cisco.com" , "Zhang, Qi Z" Message-ID: <20161006021945.GA109679@ar11-dell-r730-02-jeff.jf.intel.com> References: <1468515542-39207-2-git-send-email-jeffrey.b.shaw@intel.com> <1475712772-105327-1-git-send-email-jeffrey.b.shaw@intel.com> <1475712772-105327-2-git-send-email-jeffrey.b.shaw@intel.com> <4341B239C0EFF9468EE453F9E9F4604D3A387BDA@shsmsx102.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4341B239C0EFF9468EE453F9E9F4604D3A387BDA@shsmsx102.ccr.corp.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [dpdk-dev] [PATCH v2 2/2] i40e: Enable bad checksum flags in i40e vPMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Oct 2016 02:22:48 -0000 On Wed, Oct 05, 2016 at 04:57:28PM -0700, Chen, Jing D wrote: > Hi, > > > -----Original Message----- > > From: Shaw, Jeffrey B > > Sent: Wednesday, October 5, 2016 5:13 PM > > To: dev@dpdk.org > > Cc: Zhang, Helin ; Wu, Jingjing > > ; damarion@cisco.com; Zhang, Qi Z > > ; Chen, Jing D > > Subject: [PATCH v2 2/2] i40e: Enable bad checksum flags in i40e vPMD > > > > From: Damjan Marion > > > > Decode the checksum flags from the rx descriptor, setting the appropriate bit > > in the mbuf ol_flags field when the flag indicates a bad checksum. > > > > Signed-off-by: Damjan Marion > > Signed-off-by: Jeff Shaw > > --- > > drivers/net/i40e/i40e_rxtx_vec.c | 48 +++++++++++++++++++++++--------------- > > -- > > 1 file changed, 28 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_rxtx_vec.c > > b/drivers/net/i40e/i40e_rxtx_vec.c > > index 6c63141..d2267ad 100644 > > --- a/drivers/net/i40e/i40e_rxtx_vec.c > > +++ b/drivers/net/i40e/i40e_rxtx_vec.c > > @@ -138,19 +138,14 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq) static > > inline void desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts) { > > - __m128i vlan0, vlan1, rss; > > - union { > > - uint16_t e[4]; > > - uint64_t dword; > > - } vol; > > + __m128i vlan0, vlan1, rss, l3_l4e; > > > > /* mask everything except RSS, flow director and VLAN flags > > * bit2 is for VLAN tag, bit11 for flow director indication > > * bit13:12 for RSS indication. > > */ > > - const __m128i rss_vlan_msk = _mm_set_epi16( > > - 0x0000, 0x0000, 0x0000, 0x0000, > > - 0x3804, 0x3804, 0x3804, 0x3804); > > + const __m128i rss_vlan_msk = _mm_set_epi32( > > + 0x1c03004, 0x1c03004, 0x1c03004, 0x1c03004); Mask is wrong here. Should be 0x1c03804, ..., etc. > > > > /* map rss and vlan type to rss hash and vlan flag */ > > const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0, @@ -163,23 > > +158,36 @@ desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts) > > PKT_RX_RSS_HASH | PKT_RX_FDIR, > > PKT_RX_RSS_HASH, 0, 0, > > 0, 0, PKT_RX_FDIR, 0); > > > > - vlan0 = _mm_unpackhi_epi16(descs[0], descs[1]); > > - vlan1 = _mm_unpackhi_epi16(descs[2], descs[3]); > > - vlan0 = _mm_unpacklo_epi32(vlan0, vlan1); > > + const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, > > + PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD > > | PKT_RX_IP_CKSUM_BAD, > > + PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, > > + PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD, > > + PKT_RX_EIP_CKSUM_BAD, > > + PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD, > > + PKT_RX_L4_CKSUM_BAD, > > + PKT_RX_IP_CKSUM_BAD, > > + 0); > > + > > + vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]); > > + vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]); > > + vlan0 = _mm_unpacklo_epi64(vlan0, vlan1); > > > > vlan1 = _mm_and_si128(vlan0, rss_vlan_msk); > > vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1); > > > > - rss = _mm_srli_epi16(vlan1, 11); > > + rss = _mm_srli_epi32(vlan1, 12); > > rss = _mm_shuffle_epi8(rss_flags, rss); > > My bad. Original code will use bit[13:11] to identify RSS and FDIR flag. Now > It masked bit 11 out when creating " rss_vlan_msk" and doing shift above, > while it still try to use original "rss_flags"? Good catch. I have no idea how you spotted that, and you're right, we should be shifting by 11, not 12. Also the mask needs to be updated (as you mentioned to me offline) which I noted above. Damjan, unless you object I'll send a v3 with an updated rss_vlan_msk and the 11 bit shift so we also get the Flow Director Filter Match (FLM) indication. >