From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0070.outbound.protection.outlook.com [104.47.36.70]) by dpdk.org (Postfix) with ESMTP id E25103DC for ; Thu, 15 Dec 2016 11:04:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=b/Di92dmHPsgbUVAmbmHXTTSTLbnrFA3kRKRC/rVTdQ=; b=f4bDdRMV28JvuSRSVYaIlVw06JIU/MWHCNsmHCAtoRN5UYCPqvwgJZOHzmGao7NoM4/R2wTYClSh1PDSs0Wl2L1tTU664l7mHE+L4FFediZ+7WSDF6ig2UaQvMUDzLIUO7+o0fIaCKPxJ5ZM08Q8TnqiOS6cZSzjlBgA5y1Ov10= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@cavium.com; Received: from localhost.localdomain (122.166.153.127) by BN3PR0701MB1718.namprd07.prod.outlook.com (10.163.39.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.771.8; Thu, 15 Dec 2016 10:04:44 +0000 Date: Thu, 15 Dec 2016 15:34:24 +0530 From: Jerin Jacob To: Jianbo Liu CC: , "Ananyev, Konstantin" , Thomas Monjalon , Bruce Richardson , Jan Viktorin Message-ID: <20161215100423.GA6712@localhost.localdomain> References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com> <1481680558-4003-14-git-send-email-jerin.jacob@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; 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IN NO EVENT SHALL THE COPYRIGHT > > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > + */ > > + > > +#ifndef _RTE_IO_ARM64_H_ > > +#define _RTE_IO_ARM64_H_ > > + > > +#ifdef __cplusplus > > +extern "C" { > > +#endif > > + > > +#include > > + > > +#define RTE_OVERRIDE_IO_H > > + > > +#include "generic/rte_io.h" > > +#include "rte_atomic_64.h" > > + > > +static inline __attribute__((always_inline)) uint8_t > > +__rte_arm64_readb(const volatile void *addr) > > +{ > > + uint8_t val; > > + > > + asm volatile( > > + "ldrb %w[val], [%x[addr]]" > > + : [val] "=r" (val) > > + : [addr] "r" (addr)); > > + return val; > > +} > > + > > +static inline __attribute__((always_inline)) uint16_t > > +__rte_arm64_readw(const volatile void *addr) > > +{ > > + uint16_t val; > > + > > + asm volatile( > > + "ldrh %w[val], [%x[addr]]" > > + : [val] "=r" (val) > > + : [addr] "r" (addr)); > > + return val; > > +} > > + > > +static inline __attribute__((always_inline)) uint32_t > > +__rte_arm64_readl(const volatile void *addr) > > +{ > > + uint32_t val; > > + > > + asm volatile( > > + "ldr %w[val], [%x[addr]]" > > + : [val] "=r" (val) > > + : [addr] "r" (addr)); > > + return val; > > +} > > + > > +static inline __attribute__((always_inline)) uint64_t > > +__rte_arm64_readq(const volatile void *addr) > > +{ > > + uint64_t val; > > + > > + asm volatile( > > + "ldr %x[val], [%x[addr]]" > > + : [val] "=r" (val) > > + : [addr] "r" (addr)); > > + return val; > > +} > > + > > +static inline __attribute__((always_inline)) void > > +__rte_arm64_writeb(uint8_t val, volatile void *addr) > > +{ > > + asm volatile( > > + "strb %w[val], [%x[addr]]" > > + : > > + : [val] "r" (val), [addr] "r" (addr)); > > +} > > + > > +static inline __attribute__((always_inline)) void > > +__rte_arm64_writew(uint16_t val, volatile void *addr) > > +{ > > + asm volatile( > > + "strh %w[val], [%x[addr]]" > > + : > > + : [val] "r" (val), [addr] "r" (addr)); > > +} > > + > > +static inline __attribute__((always_inline)) void > > +__rte_arm64_writel(uint32_t val, volatile void *addr) > > +{ > > + asm volatile( > > + "str %w[val], [%x[addr]]" > > + : > > + : [val] "r" (val), [addr] "r" (addr)); > > +} > > + > > +static inline __attribute__((always_inline)) void > > +__rte_arm64_writeq(uint64_t val, volatile void *addr) > > +{ > > + asm volatile( > > + "str %x[val], [%x[addr]]" > > + : > > + : [val] "r" (val), [addr] "r" (addr)); > > +} > > I'm not quite sure about these overridings. Can you explain the > benefit to do so? Better to be native if there is option. That all. Do you see any issue? or what is the real concern?