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IN NO EVENT SHALL THE COPYRIGHT > >> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > >> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > >> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > >> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > >> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > >> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > >> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > >> > + */ > >> > + > >> > +#ifndef _RTE_IO_ARM64_H_ > >> > +#define _RTE_IO_ARM64_H_ > >> > + > >> > +#ifdef __cplusplus > >> > +extern "C" { > >> > +#endif > >> > + > >> > +#include > >> > + > >> > +#define RTE_OVERRIDE_IO_H > >> > + > >> > +#include "generic/rte_io.h" > >> > +#include "rte_atomic_64.h" > >> > + > >> > +static inline __attribute__((always_inline)) uint8_t > >> > +__rte_arm64_readb(const volatile void *addr) > >> > +{ > >> > + uint8_t val; > >> > + > >> > + asm volatile( > >> > + "ldrb %w[val], [%x[addr]]" > >> > + : [val] "=r" (val) > >> > + : [addr] "r" (addr)); > >> > + return val; > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) uint16_t > >> > +__rte_arm64_readw(const volatile void *addr) > >> > +{ > >> > + uint16_t val; > >> > + > >> > + asm volatile( > >> > + "ldrh %w[val], [%x[addr]]" > >> > + : [val] "=r" (val) > >> > + : [addr] "r" (addr)); > >> > + return val; > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) uint32_t > >> > +__rte_arm64_readl(const volatile void *addr) > >> > +{ > >> > + uint32_t val; > >> > + > >> > + asm volatile( > >> > + "ldr %w[val], [%x[addr]]" > >> > + : [val] "=r" (val) > >> > + : [addr] "r" (addr)); > >> > + return val; > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) uint64_t > >> > +__rte_arm64_readq(const volatile void *addr) > >> > +{ > >> > + uint64_t val; > >> > + > >> > + asm volatile( > >> > + "ldr %x[val], [%x[addr]]" > >> > + : [val] "=r" (val) > >> > + : [addr] "r" (addr)); > >> > + return val; > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) void > >> > +__rte_arm64_writeb(uint8_t val, volatile void *addr) > >> > +{ > >> > + asm volatile( > >> > + "strb %w[val], [%x[addr]]" > >> > + : > >> > + : [val] "r" (val), [addr] "r" (addr)); > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) void > >> > +__rte_arm64_writew(uint16_t val, volatile void *addr) > >> > +{ > >> > + asm volatile( > >> > + "strh %w[val], [%x[addr]]" > >> > + : > >> > + : [val] "r" (val), [addr] "r" (addr)); > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) void > >> > +__rte_arm64_writel(uint32_t val, volatile void *addr) > >> > +{ > >> > + asm volatile( > >> > + "str %w[val], [%x[addr]]" > >> > + : > >> > + : [val] "r" (val), [addr] "r" (addr)); > >> > +} > >> > + > >> > +static inline __attribute__((always_inline)) void > >> > +__rte_arm64_writeq(uint64_t val, volatile void *addr) > >> > +{ > >> > + asm volatile( > >> > + "str %x[val], [%x[addr]]" > >> > + : > >> > + : [val] "r" (val), [addr] "r" (addr)); > >> > +} > >> > >> I'm not quite sure about these overridings. Can you explain the > >> benefit to do so? > > > > Better to be native if there is option. That all. Do you see any issue? > > or what is the real concern? > > > > I think it's the same as the generic c version after compiling. Am I right? I really don't that is the case for all the scenarios like compiler may combine two 16bit reads one 32bit read etc and which will impact on IO register access. But, I am sure the proposed scheme generates correct instruction in all the cases.