From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id E341410BFF for ; Wed, 21 Dec 2016 12:03:38 +0100 (CET) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 21 Dec 2016 03:03:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,383,1477983600"; d="scan'208";a="42126400" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.64]) by orsmga004.jf.intel.com with SMTP; 21 Dec 2016 03:03:33 -0800 Received: by (sSMTP sendmail emulation); Wed, 21 Dec 2016 11:03:32 +0000 Date: Wed, 21 Dec 2016 11:03:32 +0000 From: Bruce Richardson To: Jerin Jacob Cc: Jianbo Liu , dev@dpdk.org, helin.zhang@intel.com, konstantin.ananyev@intel.com Message-ID: <20161221110331.GA9108@bricha3-MOBL3.ger.corp.intel.com> References: <1482127758-4904-1-git-send-email-jianbo.liu@linaro.org> <1482127758-4904-2-git-send-email-jianbo.liu@linaro.org> <20161221100848.GA4506@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161221100848.GA4506@localhost.localdomain> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.7.1 (2016-10-04) Subject: Re: [dpdk-dev] [PATCH 2/2] net/ixgbe: calculate correct number of received packets for ARM NEON-version vPMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Dec 2016 11:03:39 -0000 On Wed, Dec 21, 2016 at 03:38:51PM +0530, Jerin Jacob wrote: > On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote: > > Hi Jianbo, > > > vPMD will check 4 descriptors in one time, but the statuses are not consistent > > because the memory allocated for RX descriptors is cacheable huagepage. > Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages? This is not a problem on IA, because the instruction ordering rules on IA guarantee that the reads will be done in the correct program order, and we never get stale cache data. /Bruce