From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f48.google.com (mail-pg0-f48.google.com [74.125.83.48]) by dpdk.org (Postfix) with ESMTP id F1691100F for ; Sat, 21 Jan 2017 00:51:06 +0100 (CET) Received: by mail-pg0-f48.google.com with SMTP id 194so27219831pgd.2 for ; Fri, 20 Jan 2017 15:51:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IEsCGEt+Kp2/OJhp13rs3W+l1hieM45S574cNfbq5kw=; b=Ws36LSvy1CeH08dkwx5YowNp1AUB5e7byrYCsJv+UkNUqct+ozpiutkO2n6J41uobH wIL9L5Oa0Kz3aLwRNwGQZf3Veq0uP7ikdz5M0fV6v//MJWkUiAI9zwoGNaLJWuE6gNDZ Nj7/c9AAWfbdFHlnu+53c4B42pE+yiX0w701AfR+cQO82h0p34L/SH1J5Ts/7dkMIROv a8PIagX6jFuI6KoyWxWSMJlRogA8Jkf/IoL2ZqiEtqL3W9tR9zEbY2NreffKQLLD9y7r mfYYmOV5X+EYx8NkRmCwD2Nxczx2dZTOLmMjY4oo1MNeMxOHRtfb6J1EHMlfbUABAW/6 UR7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IEsCGEt+Kp2/OJhp13rs3W+l1hieM45S574cNfbq5kw=; b=nOKXk6DrrgbIuDxB/fBpiDONdqlmaWDyWPL5BevIyd1wgOp55qgJxNvgFYMdHxeGRr POgRwxhU9wNBnaoyZyE4TOf/RgVzhJCrkOUXfgJa8HUrI7MIKjABK6JBDkCV+Cnt64Wu sYM0TjO84jf3de7UGN3sq2NJSkdSLU9oWkf3x+ivVd86IqGTUsAaymlv3YaH0783EfLa NFc8Jv3eKARcUcUwKc2uGgAWqKvN+g4S+//8urokPuFpgzHndGT1a0QdE2nljmgyiw7C g6DBn3UYu/9UoOk8GFlLd/LUpBnpyK2HB0ZSZNHQrZ+H+tfZNULf6cOM1ydB3aeqW6Oa 2ICQ== X-Gm-Message-State: AIkVDXJx6/ymcy7XNRThm7LSe177TcJbJQF9I9zIf3VDZtuQwX9hVnFBp92OsibMtiZ6aw== X-Received: by 10.84.130.99 with SMTP id 90mr25335560plc.167.1484956266186; Fri, 20 Jan 2017 15:51:06 -0800 (PST) Received: from xeon-e3 (204-195-18-65.wavecable.com. [204.195.18.65]) by smtp.gmail.com with ESMTPSA id 18sm19420740pgf.28.2017.01.20.15.51.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Jan 2017 15:51:05 -0800 (PST) Date: Fri, 20 Jan 2017 15:50:58 -0800 From: Stephen Hemminger To: David Su Cc: dev@dpdk.org Message-ID: <20170120155058.5177efc4@xeon-e3> In-Reply-To: <1484953699-3156-1-git-send-email-david.w.su@intel.com> References: <1484953699-3156-1-git-send-email-david.w.su@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] igb_uio: use non-threaded ISR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2017 23:51:07 -0000 On Fri, 20 Jan 2017 15:08:19 -0800 David Su wrote: > This eliminates the overhead of a task switch when an interrupt arrives. > > Signed-off-by: David Su > --- > lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > index df41e45..9338e14 100644 > --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > @@ -382,6 +382,7 @@ igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) > msix_entry.entry = 0; > if (pci_enable_msix(dev, &msix_entry, 1) == 0) { > dev_dbg(&dev->dev, "using MSI-X"); > + udev->info.irq_flags = IRQF_NO_THREAD; > udev->info.irq = msix_entry.vector; > udev->mode = RTE_INTR_MODE_MSIX; > break; > @@ -390,7 +391,7 @@ igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) > case RTE_INTR_MODE_LEGACY: > if (pci_intx_mask_supported(dev)) { > dev_dbg(&dev->dev, "using INTX"); > - udev->info.irq_flags = IRQF_SHARED; > + udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD; > udev->info.irq = dev->irq; > udev->mode = RTE_INTR_MODE_LEGACY; > break; Since interrupts are only used for link state transistions with igb_uio, I can't see how the overhead of task switch would matter.