From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id B355A5927 for ; Tue, 7 Mar 2017 12:33:19 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Mar 2017 03:33:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,258,1484035200"; d="scan'208";a="831864187" Received: from sivswdev01.ir.intel.com ([10.237.217.45]) by FMSMGA003.fm.intel.com with ESMTP; 07 Mar 2017 03:32:58 -0800 From: Bruce Richardson To: olivier.matz@6wind.com Cc: jerin.jacob@caviumnetworks.com, dev@dpdk.org, Bruce Richardson Date: Tue, 7 Mar 2017 11:32:04 +0000 Message-Id: <20170307113217.11077-2-bruce.richardson@intel.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20170307113217.11077-1-bruce.richardson@intel.com> References: <20170223172407.27664-1-bruce.richardson@intel.com> <20170307113217.11077-1-bruce.richardson@intel.com> Subject: [dpdk-dev] [PATCH v2 01/14] ring: remove split cacheline build setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Mar 2017 11:33:20 -0000 Users compiling DPDK should not need to know or care about the arrangement of cachelines in the rte_ring structure. Therefore just remove the build option and set the structures to be always split. On platforms with 64B cachelines, for improved performance use 128B rather than 64B alignment since it stops the producer and consumer data being on adjacent cachelines. Signed-off-by: Bruce Richardson --- V2: Limit the cacheline * 2 alignment to platforms with < 128B line size --- config/common_base | 1 - doc/guides/rel_notes/release_17_05.rst | 6 ++++++ lib/librte_ring/rte_ring.c | 2 -- lib/librte_ring/rte_ring.h | 16 ++++++++++------ 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/config/common_base b/config/common_base index aeee13e..099ffda 100644 --- a/config/common_base +++ b/config/common_base @@ -448,7 +448,6 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # CONFIG_RTE_LIBRTE_RING=y CONFIG_RTE_LIBRTE_RING_DEBUG=n -CONFIG_RTE_RING_SPLIT_PROD_CONS=n CONFIG_RTE_RING_PAUSE_REP_COUNT=0 # diff --git a/doc/guides/rel_notes/release_17_05.rst b/doc/guides/rel_notes/release_17_05.rst index e25ea9f..ea45e0c 100644 --- a/doc/guides/rel_notes/release_17_05.rst +++ b/doc/guides/rel_notes/release_17_05.rst @@ -110,6 +110,12 @@ API Changes Also, make sure to start the actual text at the margin. ========================================================= +* **Reworked rte_ring library** + + The rte_ring library has been reworked and updated. The following changes + have been made to it: + + * removed the build-time setting ``CONFIG_RTE_RING_SPLIT_PROD_CONS`` ABI Changes ----------- diff --git a/lib/librte_ring/rte_ring.c b/lib/librte_ring/rte_ring.c index ca0a108..4bc6da1 100644 --- a/lib/librte_ring/rte_ring.c +++ b/lib/librte_ring/rte_ring.c @@ -127,10 +127,8 @@ rte_ring_init(struct rte_ring *r, const char *name, unsigned count, /* compilation-time checks */ RTE_BUILD_BUG_ON((sizeof(struct rte_ring) & RTE_CACHE_LINE_MASK) != 0); -#ifdef RTE_RING_SPLIT_PROD_CONS RTE_BUILD_BUG_ON((offsetof(struct rte_ring, cons) & RTE_CACHE_LINE_MASK) != 0); -#endif RTE_BUILD_BUG_ON((offsetof(struct rte_ring, prod) & RTE_CACHE_LINE_MASK) != 0); #ifdef RTE_LIBRTE_RING_DEBUG diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index 72ccca5..399ae3b 100644 --- a/lib/librte_ring/rte_ring.h +++ b/lib/librte_ring/rte_ring.h @@ -139,6 +139,14 @@ struct rte_ring_debug_stats { struct rte_memzone; /* forward declaration, so as not to require memzone.h */ +#if RTE_CACHE_LINE_SIZE < 128 +#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2) +#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2) +#else +#define PROD_ALIGN RTE_CACHE_LINE_SIZE +#define CONS_ALIGN RTE_CACHE_LINE_SIZE +#endif + /** * An RTE ring structure. * @@ -168,7 +176,7 @@ struct rte_ring { uint32_t mask; /**< Mask (size-1) of ring. */ volatile uint32_t head; /**< Producer head. */ volatile uint32_t tail; /**< Producer tail. */ - } prod __rte_cache_aligned; + } prod __rte_aligned(PROD_ALIGN); /** Ring consumer status. */ struct cons { @@ -177,11 +185,7 @@ struct rte_ring { uint32_t mask; /**< Mask (size-1) of ring. */ volatile uint32_t head; /**< Consumer head. */ volatile uint32_t tail; /**< Consumer tail. */ -#ifdef RTE_RING_SPLIT_PROD_CONS - } cons __rte_cache_aligned; -#else - } cons; -#endif + } cons __rte_aligned(CONS_ALIGN); #ifdef RTE_LIBRTE_RING_DEBUG struct rte_ring_debug_stats stats[RTE_MAX_LCORE]; -- 2.9.3