Re: [dpdk-dev] [PATCH v5 06/20] event/sw: add support for event queues

[Jerin Jacob <jerin.jacob@caviumnetworks.com>]

On Fri, Mar 24, 2017 at 04:53:01PM +0000, Harry van Haaren wrote:
> From: Bruce Richardson <bruce.richardson@intel.com>
> 
> Add in the data structures for the event queues, and the eventdev
> functions to create and destroy those queues.
> 
> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
> ---
>  drivers/event/sw/iq_ring.h  | 176 ++++++++++++++++++++++++++++++++++++++++++++
>  drivers/event/sw/sw_evdev.c | 166 +++++++++++++++++++++++++++++++++++++++++
>  drivers/event/sw/sw_evdev.h |   5 ++
>  3 files changed, 347 insertions(+)
>  create mode 100644 drivers/event/sw/iq_ring.h
> 
> diff --git a/drivers/event/sw/iq_ring.h b/drivers/event/sw/iq_ring.h
> new file mode 100644
> index 0000000..d480d15
> --- /dev/null
> +++ b/drivers/event/sw/iq_ring.h
> @@ -0,0 +1,176 @@
> +/*-
> + *   BSD LICENSE
> + *
> + *   Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
> + *
> + *   Redistribution and use in source and binary forms, with or without
> + *   modification, are permitted provided that the following conditions
> + *   are met:
> + *
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *       notice, this list of conditions and the following disclaimer in
> + *       the documentation and/or other materials provided with the
> + *       distribution.
> + *     * Neither the name of Intel Corporation nor the names of its
> + *       contributors may be used to endorse or promote products derived
> + *       from this software without specific prior written permission.
> + *
> + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/*
> + * Ring structure definitions used for the internal ring buffers of the
> + * SW eventdev implementation. These are designed for single-core use only.
> + */

Plan is to replace this file with generic rte_ring once Bruce's ring
rework[1] comes in master branch. Right ?

[1] http://dpdk.org/ml/archives/dev/2017-March/061372.html

> +#ifndef _IQ_RING_
> +#define _IQ_RING_
> +
> +#include <stdint.h>
> +
> +#include <rte_common.h>
> +#include <rte_memory.h>

> +++ b/drivers/event/sw/sw_evdev.c
> @@ -38,12 +38,176 @@
>  #include <rte_ring.h>
>  
>  #include "sw_evdev.h"
> +#include "iq_ring.h"
>  
>  #define EVENTDEV_NAME_SW_PMD event_sw
>  #define NUMA_NODE_ARG "numa_node"
>  #define SCHED_QUANTA_ARG "sched_quanta"
>  #define CREDIT_QUANTA_ARG "credit_quanta"
>  
> +static int32_t
> +qid_init(struct sw_evdev *sw, unsigned int idx, int type,
> +		const struct rte_event_queue_conf *queue_conf)
> +{
> +	unsigned int i;
> +	int dev_id = sw->data->dev_id;
> +	int socket_id = sw->data->socket_id;
> +	char buf[IQ_RING_NAMESIZE];
> +	struct sw_qid *qid = &sw->qids[idx];
> +
> +	for (i = 0; i < SW_IQS_MAX; i++) {

Just for my understanding, Are 4(SW_IQS_MAX) iq rings created to address
different priority for each enqueue operation? What is the significance of
4(SW_IQS_MAX) here?

> +		snprintf(buf, sizeof(buf), "q_%u_iq_%d", idx, i);
> +		qid->iq[i] = iq_ring_create(buf, socket_id);
> +		if (!qid->iq[i]) {
> +			SW_LOG_DBG("ring create failed");
> +			goto cleanup;
> +		}
> +	}
> +
> +
> +static int
> +sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
> +		const struct rte_event_queue_conf *conf)
> +{
> +	int type;
> +
> +	switch (conf->event_queue_cfg) {
> +	case RTE_EVENT_QUEUE_CFG_SINGLE_LINK:
> +		type = SW_SCHED_TYPE_DIRECT;
> +		break;

event_queue_cfg is a bitmap. It is valid to have
RTE_EVENT_QUEUE_CFG_SINGLE_LINK | RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY.
i.e An atomic schedule type queue and it has only one port linked to
dequeue the events.
So in the above context, The switch case is not correct. i.e
it goes to the default condition. Right?
Is this intentional?

If I understand it correctly, Based on the use case(grouped based event
pipelining), you have shared in
the documentation patch. RTE_EVENT_QUEUE_CFG_SINGLE_LINK used for last
stage(last queue). One option is if SW PMD cannot support
RTE_EVENT_QUEUE_CFG_SINGLE_LINK | RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY mode
then even tough application sets the RTE_EVENT_QUEUE_CFG_SINGLE_LINK |
RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY, driver can ignore
RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY. But I am not sure the case where
application sets RTE_EVENT_QUEUE_CFG_SINGLE_LINK in the middle of the pipeline.

Thoughts?

> +	case RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY:
> +		type = RTE_SCHED_TYPE_ATOMIC;
> +		break;
> +	case RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:
> +		type = RTE_SCHED_TYPE_ORDERED;
> +		break;
> +	case RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:
> +		type = RTE_SCHED_TYPE_PARALLEL;
> +		break;
> +	case RTE_EVENT_QUEUE_CFG_ALL_TYPES:
> +		SW_LOG_ERR("QUEUE_CFG_ALL_TYPES not supported\n");
> +		return -ENOTSUP;
> +	default:
> +		SW_LOG_ERR("Unknown queue type %d requested\n",
> +			   conf->event_queue_cfg);
> +		return -EINVAL;
> +	}
> +
> +	struct sw_evdev *sw = sw_pmd_priv(dev);
> +	return qid_init(sw, queue_id, type, conf);
> +}