From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from proxy.6wind.com (host.76.145.23.62.rev.coltfrance.com [62.23.145.76]) by dpdk.org (Postfix) with ESMTP id D116569D8 for ; Wed, 29 Mar 2017 10:36:19 +0200 (CEST) Received: from glumotte.dev.6wind.com (unknown [10.16.0.195]) by proxy.6wind.com (Postfix) with ESMTP id 2C3E425D39; Wed, 29 Mar 2017 10:36:14 +0200 (CEST) From: Olivier Matz To: dev@dpdk.org, thomas.monjalon@6wind.com, konstantin.ananyev@intel.com, wenzhuo.lu@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com Cc: ferruh.yigit@intel.com, bruce.richardson@intel.com, venky.venkatesan@intel.com, arybchenko@solarflare.com, qiming.yang@intel.com Date: Wed, 29 Mar 2017 10:36:31 +0200 Message-Id: <20170329083633.15626-5-olivier.matz@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170329083633.15626-1-olivier.matz@6wind.com> References: <1488902393-7237-1-git-send-email-olivier.matz@6wind.com> <20170329083633.15626-1-olivier.matz@6wind.com> Subject: [dpdk-dev] [PATCH v3 4/6] net/e1000: implement descriptor status API (em) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Mar 2017 08:36:20 -0000 Signed-off-by: Olivier Matz --- doc/guides/nics/features/e1000.ini | 2 ++ drivers/net/e1000/e1000_ethdev.h | 3 +++ drivers/net/e1000/em_ethdev.c | 2 ++ drivers/net/e1000/em_rxtx.c | 51 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/doc/guides/nics/features/e1000.ini b/doc/guides/nics/features/e1000.ini index 3aed7d709..6a7c6c7d7 100644 --- a/doc/guides/nics/features/e1000.ini +++ b/doc/guides/nics/features/e1000.ini @@ -21,6 +21,8 @@ VLAN offload = Y QinQ offload = Y L3 checksum offload = Y L4 checksum offload = Y +Rx Descriptor Status = Y +Tx Descriptor Status = Y Basic stats = Y BSD nic_uio = Y Linux UIO = Y diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h index cb760e986..8352d0a79 100644 --- a/drivers/net/e1000/e1000_ethdev.h +++ b/drivers/net/e1000/e1000_ethdev.h @@ -380,6 +380,9 @@ uint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev, int eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset); +int eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset); +int eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset); + int eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c index e76e34bbe..7110af344 100644 --- a/drivers/net/e1000/em_ethdev.c +++ b/drivers/net/e1000/em_ethdev.c @@ -205,6 +205,8 @@ static const struct eth_dev_ops eth_em_ops = { .rx_queue_release = eth_em_rx_queue_release, .rx_queue_count = eth_em_rx_queue_count, .rx_descriptor_done = eth_em_rx_descriptor_done, + .rx_descriptor_status = eth_em_rx_descriptor_status, + .tx_descriptor_status = eth_em_tx_descriptor_status, .tx_queue_setup = eth_em_tx_queue_setup, .tx_queue_release = eth_em_tx_queue_release, .rx_queue_intr_enable = eth_em_rx_queue_intr_enable, diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c index a265cb41c..31819c5bd 100644 --- a/drivers/net/e1000/em_rxtx.c +++ b/drivers/net/e1000/em_rxtx.c @@ -1468,6 +1468,57 @@ eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset) return !!(rxdp->status & E1000_RXD_STAT_DD); } +int +eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + struct em_rx_queue *rxq = rx_queue; + volatile uint8_t *status; + uint32_t desc; + + if (unlikely(offset >= rxq->nb_rx_desc)) + return -EINVAL; + + if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + + desc = rxq->rx_tail + offset; + if (desc >= rxq->nb_rx_desc) + desc -= rxq->nb_rx_desc; + + status = &rxq->rx_ring[desc].status; + if (*status & E1000_RXD_STAT_DD) + return RTE_ETH_RX_DESC_DONE; + + return RTE_ETH_RX_DESC_AVAIL; +} + +int +eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + struct em_tx_queue *txq = tx_queue; + volatile uint8_t *status; + uint32_t desc; + + if (unlikely(offset >= txq->nb_tx_desc)) + return -EINVAL; + + desc = txq->tx_tail + offset; + /* go to next desc that has the RS bit */ + desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * + txq->tx_rs_thresh; + if (desc >= txq->nb_tx_desc) { + desc -= txq->nb_tx_desc; + if (desc >= txq->nb_tx_desc) + desc -= txq->nb_tx_desc; + } + + status = &txq->tx_ring[desc].upper.fields.status; + if (*status & E1000_TXD_STAT_DD) + return RTE_ETH_TX_DESC_DONE; + + return RTE_ETH_TX_DESC_FULL; +} + void em_dev_clear_queues(struct rte_eth_dev *dev) { -- 2.11.0