From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id E55C82BB0 for ; Tue, 18 Apr 2017 12:22:33 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shahafs@mellanox.com) with ESMTPS (AES256-SHA encrypted); 18 Apr 2017 13:22:30 +0300 Received: from unicorn01.mtl.labs.mlnx (unicorn01.mtl.labs.mlnx [10.7.12.62]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v3IAMU1d017801; Tue, 18 Apr 2017 13:22:30 +0300 Received: from unicorn01.mtl.labs.mlnx (localhost [127.0.0.1]) by unicorn01.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id v3IAMUBQ146019; Tue, 18 Apr 2017 13:22:30 +0300 Received: (from root@localhost) by unicorn01.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id v3IAMUTF146018; Tue, 18 Apr 2017 13:22:30 +0300 From: Shahaf Shuler To: adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com Cc: dev@dpdk.org, Raslan Darawsheh Date: Tue, 18 Apr 2017 13:22:28 +0300 Message-Id: <20170418102228.145971-2-shahafs@mellanox.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170418102228.145971-1-shahafs@mellanox.com> References: <20170416074640.171390-1-shahafs@mellanox.com> <20170418102228.145971-1-shahafs@mellanox.com> Subject: [dpdk-dev] [PATCH v2 2/2] net/mlx5: fix PMD specific parameters defaults X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Apr 2017 10:22:34 -0000 With the Enhanced multi packet send addition, the defaults were made in order to get the maximum out of the box performance. Features like tso, don't use the enhanced send, however the defaults are still valid. This cause Tx queue creation to fail. Fixes: aea00c008140 ("net/mlx5: add hardware TSO support") Signed-off-by: Shahaf Shuler Signed-off-by: Raslan Darawsheh Acked-by: Yongseok Koh --- on v2: * changed MLX5_UNSET to MLX5_ARG_UNSET. --- drivers/net/mlx5/mlx5.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 78724a1bb..c48fea82b 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -610,13 +610,6 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) priv->pd = pd; priv->mtu = ETHER_MTU; priv->mps = mps; /* Enable MPW by default if supported. */ - /* Set default values for Enhanced MPW, a.k.a MPWv2. */ - if (mps == MLX5_MPW_ENHANCED) { - priv->mpw_hdr_dseg = 0; - priv->txqs_inline = MLX5_EMPW_MIN_TXQS; - priv->inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN; - priv->txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE; - } priv->cqe_comp = 1; /* Enable compression by default. */ priv->tunnel_en = tunnel_en; err = mlx5_args(&args, pci_dev->device.devargs); @@ -688,6 +681,17 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) INFO("%sMPS is %s", priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); + /* Set default values for Enhanced MPW, a.k.a MPWv2. */ + if (priv->mps == MLX5_MPW_ENHANCED) { + if (args.txqs_inline == MLX5_ARG_UNSET) + priv->txqs_inline = MLX5_EMPW_MIN_TXQS; + if (args.inline_max_packet_sz == MLX5_ARG_UNSET) + priv->inline_max_packet_sz = + MLX5_EMPW_MAX_INLINE_LEN; + if (args.txq_inline == MLX5_ARG_UNSET) + priv->txq_inline = MLX5_WQE_SIZE_MAX - + MLX5_WQE_SIZE; + } /* Allocate and register default RSS hash keys. */ priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, sizeof((*priv->rss_conf)[0]), 0); -- 2.12.0