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Wed, 26 Apr 2017 16:29:46 +0000 From: Jerin Jacob To: dev@dpdk.org Cc: thomas@monjalon.net, jianbo.liu@linaro.org, hemant.agrawal@nxp.com, christian.ehrhardt@canonical.com, Jerin Jacob Date: Wed, 26 Apr 2017 21:59:19 +0530 Message-Id: <20170426162919.15397-1-jerin.jacob@caviumnetworks.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: PN1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (10.174.144.160) To BN3PR0701MB1718.namprd07.prod.outlook.com (10.163.39.17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cb2b67b1-c92f-4470-6aa2-08d48cc174d4 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(201703131423075)(201703031133081); SRVR:BN3PR0701MB1718; X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1718; 3:Z9/bMUouvY6n2MM1fT+3eTUQlZs1bYQDHkSyZ4IS3a3jGnmjyQH4FJfJA0J6+bz+Leqh8P6LEbpFeGKDnypaxwYyfSqyYuMMG46VaFcTTMCW/ueU+Qn63ok3ejKw8EXFyBno6xK2W8HESocC+5TgzzEcPgGzMhhuqBiWzHHk+X2j+Z6HNpbC2bbLNbTxikAVHX3SxJPbqp+UXJQs90exgkZTwkWa17fPt0I8vpqEGRkFbCCVaHEX4BDQ+HMIlP7vVAM3CIdEIGlPbkTx3rsWIDf19VKJSxShb4GLkUbjOo6SeAWML01RK26IRhW3sDLjP3OWK15ZrQTfSRjMGwRwxA==; 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Setting to the maximum available cache line size in generic config to address minimum DMA alignment across all arm64 implementations. Increasing the cacheline size has no negative impact to cache invalidation on systems with a smaller cache line. The need for the minimum DMA alignment has impact on functional aspects of the platform so default config should cater the functional aspects. There is an impact on memory usage with this scheme, but that's not too important for the single image arm64 distribution use case. The arm64 linux kernel followed the similar approach for single arm64 image use case. http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h Signed-off-by: Jerin Jacob --- config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++ config/defconfig_arm64-dpaa2-linuxapp-gcc | 1 + config/defconfig_arm64-xgene1-linuxapp-gcc | 1 + 3 files changed, 7 insertions(+) diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc index 65888cef1..0faa2d3a3 100644 --- a/config/defconfig_arm64-armv8a-linuxapp-gcc +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc @@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y CONFIG_RTE_TOOLCHAIN="gcc" CONFIG_RTE_TOOLCHAIN_GCC=y +#Maximum available cache line size in arm64 implementations. Setting to maximum +#available cache line size in generic config to address minimum DMA alignment +#across all arm64 implementations. +CONFIG_RTE_CACHE_LINE_SIZE=128 + CONFIG_RTE_EAL_IGB_UIO=n CONFIG_RTE_LIBRTE_FM10K_PMD=n diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc index 010cb8092..314a0eceb 100644 --- a/config/defconfig_arm64-dpaa2-linuxapp-gcc +++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc @@ -41,6 +41,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd" # CONFIG_RTE_MAX_LCORE=8 CONFIG_RTE_MAX_NUMA_NODES=1 +CONFIG_RTE_CACHE_LINE_SIZE=64 CONFIG_RTE_PKTMBUF_HEADROOM=256 diff --git a/config/defconfig_arm64-xgene1-linuxapp-gcc b/config/defconfig_arm64-xgene1-linuxapp-gcc index f096166b7..d8e544728 100644 --- a/config/defconfig_arm64-xgene1-linuxapp-gcc +++ b/config/defconfig_arm64-xgene1-linuxapp-gcc @@ -32,3 +32,4 @@ #include "defconfig_arm64-armv8a-linuxapp-gcc" CONFIG_RTE_MACHINE="xgene1" +CONFIG_RTE_CACHE_LINE_SIZE=64 -- 2.12.2