From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 4F6E19E3 for ; Fri, 28 Apr 2017 10:15:59 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP; 28 Apr 2017 01:15:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,387,1488873600"; d="scan'208";a="1124367481" Received: from sivswdev01.ir.intel.com ([10.237.217.45]) by orsmga001.jf.intel.com with ESMTP; 28 Apr 2017 01:15:57 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson Date: Fri, 28 Apr 2017 09:15:51 +0100 Message-Id: <20170428081551.28954-1-bruce.richardson@intel.com> X-Mailer: git-send-email 2.8.4 Subject: [dpdk-dev] [PATCH] eal: fix 64bit address alignment in 32-bit builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 08:15:59 -0000 On i686 builds, the uint64_t type is 64-bits in size but is aligned to 32-bits only. This causes mbuf fields for rearm_data to not be 16-byte aligned on 32-bit builds, which causes errors with some vector PMDs which expect the rearm data to be aligned as on 64-bit. Given that we cannot use the extra space in the data structures anyway, as it's already used on 64-bit builds, we can just force alignment of physical address structure members to 8-bytes in all cases. This has no effect on 64-bit systems, but fixes the updated PMDs on 32-bit. Fixes: f4356d7ca168 ("net/i40e: eliminate mbuf write on rearm") Fixes: f160666a1073 ("net/ixgbe: eliminate mbuf write on rearm") Signed-off-by: Bruce Richardson --- lib/librte_eal/common/include/rte_memory.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h index 4aa5d1f..ad14875 100644 --- a/lib/librte_eal/common/include/rte_memory.h +++ b/lib/librte_eal/common/include/rte_memory.h @@ -98,7 +98,8 @@ enum rte_page_sizes { */ #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) -typedef uint64_t phys_addr_t; /**< Physical address definition. */ +/** Physical address definition. */ +typedef uint64_t phys_addr_t __rte_aligned(sizeof(uint64_t)); #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) /** -- 2.9.3