From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id ED59B3B5 for ; Fri, 28 Apr 2017 11:26:22 +0200 (CEST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Apr 2017 02:26:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,387,1488873600"; d="scan'208";a="93218826" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.133]) by orsmga005.jf.intel.com with SMTP; 28 Apr 2017 02:26:18 -0700 Received: by (sSMTP sendmail emulation); Fri, 28 Apr 2017 10:26:18 +0100 Date: Fri, 28 Apr 2017 10:26:17 +0100 From: Bruce Richardson To: Thomas Monjalon Cc: Qi Zhang , dev@dpdk.org, jingjing.wu@intel.com, helin.zhang@intel.com, wenzhuo.lu@intel.com, jing.d.chen@intel.com, ferruh.yigit@intel.com Message-ID: <20170428092617.GA14648@bricha3-MOBL3.ger.corp.intel.com> References: <20170424145848.18544-1-qi.z.zhang@intel.com> <20170427070107.65465-1-qi.z.zhang@intel.com> <20170427092539.GA7544@bricha3-MOBL3.ger.corp.intel.com> <1655942.nOeDIEQQQZ@xps> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1655942.nOeDIEQQQZ@xps> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.8.0 (2017-02-23) Subject: Re: [dpdk-dev] [PATCH 0/3 v2] disable vector PMD for i686 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 09:26:23 -0000 On Fri, Apr 28, 2017 at 11:14:24AM +0200, Thomas Monjalon wrote: > 27/04/2017 11:25, Bruce Richardson: > > On Thu, Apr 27, 2017 at 03:01:04AM -0400, Qi Zhang wrote: > > > Vector PMD is not designed for i686 orginally, but it still can be active > > > with i686 compile option. > > > Below are observed failure when vPMD is invovled on i686 > > > (but may not limited to) > > > > > > 1) memory overwrite when assign 2 mbuf points to rx return points. > > > _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2) > > > > Is this a serious issue that prevents us using the driver? I think it's been > > in the code for quite some time. Can it not be relatively easily fixed for > > 32-bit builds? > > > > > > > > 2) rearm_data is not 16 bytes aligned that cause general-protection exception > > > _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0); > > > > > > > Good catch. I think this is also an easy fix. My preferred fix is to > > explicitly align the rearm data on a 16-byte boundary. It would add some > > padding to the middle of cacheline0 of the mbuf, but given that we > > explicitly move other data to cacheline1, we will have padding on 32-bit > > anyway, be it in the middle or the end of the mbuf cachelines. > > > > > So the patch set will exclude Vector PMD from compile with i686 configure. > > Please try to fix the drivers instead of turning them off. The patch for alignment of physical addresses should fix these issues, removing the need for these patches. /Bruce