From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id A85CB3B5 for ; Fri, 28 Apr 2017 12:14:52 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP; 28 Apr 2017 03:14:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,387,1488873600"; d="scan'208";a="962114250" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.133]) by orsmga003.jf.intel.com with SMTP; 28 Apr 2017 03:14:49 -0700 Received: by (sSMTP sendmail emulation); Fri, 28 Apr 2017 11:14:48 +0100 Date: Fri, 28 Apr 2017 11:14:48 +0100 From: Bruce Richardson To: Olivier Matz Cc: Thomas Monjalon , dev@dpdk.org Message-ID: <20170428101448.GA25256@bricha3-MOBL3.ger.corp.intel.com> References: <20170428081551.28954-1-bruce.richardson@intel.com> <1797441.atIi8ZZIaG@xps> <20170428090306.GA25692@bricha3-MOBL3.ger.corp.intel.com> <2039188.oPr2FiSFIW@xps> <20170428093202.GB14648@bricha3-MOBL3.ger.corp.intel.com> <20170428115654.58f14b0d@platinum> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170428115654.58f14b0d@platinum> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.8.0 (2017-02-23) Subject: Re: [dpdk-dev] [PATCH] eal: fix 64bit address alignment in 32-bit builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 10:14:53 -0000 On Fri, Apr 28, 2017 at 11:56:54AM +0200, Olivier Matz wrote: > Hi, > > On Fri, 28 Apr 2017 10:32:03 +0100, Bruce Richardson wrote: > > On Fri, Apr 28, 2017 at 11:21:27AM +0200, Thomas Monjalon wrote: > > > 28/04/2017 11:03, Bruce Richardson: > > > > On Fri, Apr 28, 2017 at 10:56:56AM +0200, Thomas Monjalon wrote: > > > > > 28/04/2017 10:15, Bruce Richardson: > > > > > > On i686 builds, the uint64_t type is 64-bits in size but is aligned to > > > > > > 32-bits only. This causes mbuf fields for rearm_data to not be 16-byte > > > > > > aligned on 32-bit builds, which causes errors with some vector PMDs which > > > > > > expect the rearm data to be aligned as on 64-bit. > > > > > > > > > > > > Given that we cannot use the extra space in the data structures anyway, as > > > > > > it's already used on 64-bit builds, we can just force alignment of physical > > > > > > address structure members to 8-bytes in all cases. This has no effect on > > > > > > 64-bit systems, but fixes the updated PMDs on 32-bit. > > > > > > > > > > I agree to align on 64-bit in mbuf. > > > > > > > > > > > Fixes: f4356d7ca168 ("net/i40e: eliminate mbuf write on rearm") > > > > > > Fixes: f160666a1073 ("net/ixgbe: eliminate mbuf write on rearm") > > > > > [...] > > > > > > --- a/lib/librte_eal/common/include/rte_memory.h > > > > > > +++ b/lib/librte_eal/common/include/rte_memory.h > > > > > > -typedef uint64_t phys_addr_t; /**< Physical address definition. */ > > > > > > +/** Physical address definition. */ > > > > > > +typedef uint64_t phys_addr_t __rte_aligned(sizeof(uint64_t)); > > > > > > > > > > Why setting this constraint for everyone? > > > > > > > > > Well, it only has an effect on 32-bit builds, and unless there is a > > > > problem, I don't see why not always align them to the extra 8 bytes. If > > > > this does cause an issue, I'm happy enough to use #ifdefs, but in the > > > > absense of a confirmed problem, I'd rather keep the code clean. > > > > > > Is it expected for everyone to have every physical addresses aligned on 64? > > > I think it can be weird for some applications. > > > Why do you think it is cleaner than adding the alignment to the mbuf fields? > > > > > I'm ok to redo the patch to only make the change to the mbuf value. > > However, when researching this, I discovered that gcc apparently already > > aligns all non-structure-member uint64_t values on an 8-byte boundary on > > 32-bit x86 anyway*. [Don't know if this also applies e.g. to 32-bit arm, > > but I wouldn't be surprised if it did.] That means the scope of this > > only applies to structures with phys_addr values, so it's not a huge > > scope. > > *Ref: https://gcc.gnu.org/ml/gcc/2009-06/msg00333.html > > > > > PS: It is yet another macro which is not rte_ prefixed. > > > > > Yes. Not going to fix that in this patch though! > > > > So, do you want a V2 to limit the alignment change to the phys_addr in > > the mbuf, rather than generally to physical addresses? I prefer the way > > I have it here, but I'm ok to change. > > Since the need comes from vector pmd, I think it's better to limit > the alignment in the mbuf. Ok, I'll do a V2. > > Also, it would be good to progressively add some compile-time BUG_ON() in > vector PMDs that have some hidden field alignment/ordering constraints. > Yes, good idea. I'll see about patching that too. /Bruce