From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f42.google.com (mail-wm0-f42.google.com [74.125.82.42]) by dpdk.org (Postfix) with ESMTP id BFD8D2C18 for ; Fri, 28 Apr 2017 11:56:56 +0200 (CEST) Received: by mail-wm0-f42.google.com with SMTP id r190so41925228wme.1 for ; Fri, 28 Apr 2017 02:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rjzpCkvE5eF5/NfZdRP52sxnw6ngJRQkf9Pw9Yb/AsM=; b=fGhOQGlIu5yaBFEuPkYyeJOypMtlDfpMwtS5CGw503V2nTty1VybFwyKRkkM3VLgtX pcm0uDJBXiUeK5cWyr2NAelcoxuIKbqkpPyKJz9HBN1qVYUYdjr/oC1VNqe3SlftcAlH 7GX7Xr04zPjn1ElVNjOKkIUW7VFYPwvtyoCB4OwTAsNC+7BQ3FNWzKtahIjsTPCU1VeQ CGBCAIs+HXhwxeQZEUtyoUIL9PYtsNh2/wjIPjbOsbe4mpOhmyl00WbIHfrk9puZ1+hZ IJ5wgxBcYMXcc0OQg05GNyzaVWDsM55zKcbUrnWsWjA0UXZBLFEfvV/W51iutAHX/a2+ VIfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjzpCkvE5eF5/NfZdRP52sxnw6ngJRQkf9Pw9Yb/AsM=; b=hEVFNQ0167jzYxYRBtFkyzWVt583jogIswt0+m3QhQJuPvxy/0WN6+HB1OJVabmK5M +0/jMPylABnUvu3b4EsfnYjWxRHYHe7R4JYT7fQveHRkoQcpIsiOW3ebcGwE3tmjyVcR mqiWnVIwG2DJYvrEnW6VhOlQJQ05PCaNXPwm5Oiplhe/0Hnu14ggr57pVE6KB2gmLfnT EJrhyS5tCzqCnVkstr/jevwQOk5/eXKVfF60JbZVAacPUlZYzYhBqfipsyVICzpBn2uU /lO7+F1pfxyzAkwe80e9ia8+oFO3uwo0yS3JL2E0mGyRPKlhd3jXCm8vEkdWB6mYqlsL 636g== X-Gm-Message-State: AN3rC/7RzHQb6N4DHvXGnJPlji4mfk0xrUS6k6nOYQOjh6lCYwS0S4CK FUJ9PgI6mgyhejl0 X-Received: by 10.28.144.1 with SMTP id s1mr4918963wmd.27.1493373416340; Fri, 28 Apr 2017 02:56:56 -0700 (PDT) Received: from platinum (2a01cb0c03c651000226b0fffeed02fc.ipv6.abo.wanadoo.fr. [2a01:cb0c:3c6:5100:226:b0ff:feed:2fc]) by smtp.gmail.com with ESMTPSA id z14sm1970219wmz.2.2017.04.28.02.56.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Apr 2017 02:56:56 -0700 (PDT) Date: Fri, 28 Apr 2017 11:56:54 +0200 From: Olivier Matz To: Bruce Richardson Cc: Thomas Monjalon , dev@dpdk.org Message-ID: <20170428115654.58f14b0d@platinum> In-Reply-To: <20170428093202.GB14648@bricha3-MOBL3.ger.corp.intel.com> References: <20170428081551.28954-1-bruce.richardson@intel.com> <1797441.atIi8ZZIaG@xps> <20170428090306.GA25692@bricha3-MOBL3.ger.corp.intel.com> <2039188.oPr2FiSFIW@xps> <20170428093202.GB14648@bricha3-MOBL3.ger.corp.intel.com> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] eal: fix 64bit address alignment in 32-bit builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 09:56:56 -0000 Hi, On Fri, 28 Apr 2017 10:32:03 +0100, Bruce Richardson wrote: > On Fri, Apr 28, 2017 at 11:21:27AM +0200, Thomas Monjalon wrote: > > 28/04/2017 11:03, Bruce Richardson: > > > On Fri, Apr 28, 2017 at 10:56:56AM +0200, Thomas Monjalon wrote: > > > > 28/04/2017 10:15, Bruce Richardson: > > > > > On i686 builds, the uint64_t type is 64-bits in size but is aligned to > > > > > 32-bits only. This causes mbuf fields for rearm_data to not be 16-byte > > > > > aligned on 32-bit builds, which causes errors with some vector PMDs which > > > > > expect the rearm data to be aligned as on 64-bit. > > > > > > > > > > Given that we cannot use the extra space in the data structures anyway, as > > > > > it's already used on 64-bit builds, we can just force alignment of physical > > > > > address structure members to 8-bytes in all cases. This has no effect on > > > > > 64-bit systems, but fixes the updated PMDs on 32-bit. > > > > > > > > I agree to align on 64-bit in mbuf. > > > > > > > > > Fixes: f4356d7ca168 ("net/i40e: eliminate mbuf write on rearm") > > > > > Fixes: f160666a1073 ("net/ixgbe: eliminate mbuf write on rearm") > > > > [...] > > > > > --- a/lib/librte_eal/common/include/rte_memory.h > > > > > +++ b/lib/librte_eal/common/include/rte_memory.h > > > > > -typedef uint64_t phys_addr_t; /**< Physical address definition. */ > > > > > +/** Physical address definition. */ > > > > > +typedef uint64_t phys_addr_t __rte_aligned(sizeof(uint64_t)); > > > > > > > > Why setting this constraint for everyone? > > > > > > > Well, it only has an effect on 32-bit builds, and unless there is a > > > problem, I don't see why not always align them to the extra 8 bytes. If > > > this does cause an issue, I'm happy enough to use #ifdefs, but in the > > > absense of a confirmed problem, I'd rather keep the code clean. > > > > Is it expected for everyone to have every physical addresses aligned on 64? > > I think it can be weird for some applications. > > Why do you think it is cleaner than adding the alignment to the mbuf fields? > > > I'm ok to redo the patch to only make the change to the mbuf value. > However, when researching this, I discovered that gcc apparently already > aligns all non-structure-member uint64_t values on an 8-byte boundary on > 32-bit x86 anyway*. [Don't know if this also applies e.g. to 32-bit arm, > but I wouldn't be surprised if it did.] That means the scope of this > only applies to structures with phys_addr values, so it's not a huge > scope. > *Ref: https://gcc.gnu.org/ml/gcc/2009-06/msg00333.html > > > PS: It is yet another macro which is not rte_ prefixed. > > > Yes. Not going to fix that in this patch though! > > So, do you want a V2 to limit the alignment change to the phys_addr in > the mbuf, rather than generally to physical addresses? I prefer the way > I have it here, but I'm ok to change. Since the need comes from vector pmd, I think it's better to limit the alignment in the mbuf. Also, it would be good to progressively add some compile-time BUG_ON() in vector PMDs that have some hidden field alignment/ordering constraints. Olivier