From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f50.google.com (mail-wm0-f50.google.com [74.125.82.50]) by dpdk.org (Postfix) with ESMTP id 18CF85A6A for ; Wed, 3 May 2017 09:32:44 +0200 (CEST) Received: by mail-wm0-f50.google.com with SMTP id w64so136714510wma.0 for ; Wed, 03 May 2017 00:32:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=FjX08FV7MHVNkglwSVRM+1eV0hAIbaeLpGbfqKa6M+g=; b=T+zJMHCfetapNMdmqDEU+ZRUGuSvVje3E/HHuaioudgXcx7VYx6zRw4//gGT6UJge7 yeeDtGGVAab26Kc+he3n4im0gTrZQ18S2ShrnpsDVAG+57LdTdBi1U2Wu7Ge+6zTl4t1 Hd+OcPpQz+sKGwwShshpU7WA2wT86O3dj/zYrqQ7GBW1dxDL8FjCD/gHPeq9Xla/wi98 S6pJJ/lfqK4OFpKt+PzRQFObiB8QmBoG9uFSbqhn4ROfa3E+S4Ijk15XwL7ZP26aVyDd 5fdfVoK5PDfEqSZfSdepIn6EFOcMaNl/IvsGrp4DjXs/rie7ZRVvmUISRGKE2S9DW10n ZNOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=FjX08FV7MHVNkglwSVRM+1eV0hAIbaeLpGbfqKa6M+g=; b=EkwvX3rajiETdS0OFNrypLz34dblPAqzY5Wlgjz+0laG1u+R/je/t7PQGmU6Bp7DhV tzxMzK/ui6yE5ypBdU2HBCyWlFtlcUSg2oGN3o/YjyP6ObSdycqQfK9+HxBVGsD+8zxR XzN40BE1ZlG/hAHazBVIJgr2MmnCnMRstJsMSO/dfQ8Rh3gQKoZWqZeiXjmLmx8pW/Dd KcfK/NFuYTdCOSJt/dPeRO+JpvJ1gYl6eRINDvGvC4Pa3XrTb/sB/TjVJoQIjfdPWdam MUEPBcpsGfeVE02nIZYhTEjywK1Uhufa2tZQnFEZa0UqtTEhlR8U6qEGc93N0zZWTG7A aXxQ== X-Gm-Message-State: AN3rC/65bsyAxqPB+wVWAl1hZvE2HgB/ykAXmJDpTScf502nc4lbU7Be y8Cy1XPThMYV3yJ0 X-Received: by 10.28.54.85 with SMTP id d82mr5618187wma.84.1493796764745; Wed, 03 May 2017 00:32:44 -0700 (PDT) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id l29sm3385361wmi.8.2017.05.03.00.32.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 May 2017 00:32:43 -0700 (PDT) Date: Wed, 3 May 2017 09:32:38 +0200 From: Adrien Mazarguil To: Shahaf Shuler Cc: nelio.laranjeiro@6wind.com, dev@dpdk.org Message-ID: <20170503073237.GJ16218@6wind.com> References: <20170503065535.188899-1-shahafs@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170503065535.188899-1-shahafs@mellanox.com> Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix Tx max inline with TSO X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 May 2017 07:32:45 -0000 On Wed, May 03, 2017 at 09:55:35AM +0300, Shahaf Shuler wrote: > When TSO is enabled, Verbs layer aggregates the TSO > inline size with the txq inline size for the Tx creation, > while the PMD takes the maximum among them. > > Fixing it by adjusting the max inline parameter before > passing to to Verbs. > > Fixes: 3f13f8c23a7c ("net/mlx5: support hardware TSO") > > Signed-off-by: Shahaf Shuler > Acked-by: Yongseok Koh > --- > drivers/net/mlx5/mlx5_txq.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c > index f80740a13..24bd8c615 100644 > --- a/drivers/net/mlx5/mlx5_txq.c > +++ b/drivers/net/mlx5/mlx5_txq.c > @@ -230,6 +230,9 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, > struct ibv_exp_cq_attr cq_attr; > } attr; > unsigned int cqe_n; > + const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER + > + (RTE_CACHE_LINE_SIZE - 1)) / > + RTE_CACHE_LINE_SIZE); > int ret = 0; > > if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { > @@ -307,16 +310,22 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, > priv->inline_max_packet_sz) + > (RTE_CACHE_LINE_SIZE - 1)) / > RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE; > + } else if (priv->tso) { > + int inline_diff = tmpl.txq.max_inline - max_tso_inline; > + > + /* Adjust inline value as Verbs aggregates > + * tso_inline and txq_inline fields. > + */ Minor nit about this comment, the coding style should match the rest of the file with "/*" alone on its own line. > + attr.init.cap.max_inline_data = inline_diff > 0 ? > + inline_diff * > + RTE_CACHE_LINE_SIZE : > + 0; > } else { > attr.init.cap.max_inline_data = > tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE; > } > } > if (priv->tso) { > - uint16_t max_tso_inline = ((MLX5_MAX_TSO_HEADER + > - (RTE_CACHE_LINE_SIZE - 1)) / > - RTE_CACHE_LINE_SIZE); > - > attr.init.max_tso_header = > max_tso_inline * RTE_CACHE_LINE_SIZE; > attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER; > -- > 2.12.0 > -- Adrien Mazarguil 6WIND