* [dpdk-dev] [PATCH 01/20] event/dpaa2: add basic build infrastructure
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-31 14:59 ` Jerin Jacob
2017-05-25 18:07 ` [dpdk-dev] [PATCH 02/20] bus/fslmc: generic framework for mc object creation Nipun Gupta
` (19 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
MAINTAINERS | 4 ++
config/defconfig_arm64-dpaa2-linuxapp-gcc | 6 ++
drivers/event/Makefile | 2 +
drivers/event/dpaa2/Makefile | 56 ++++++++++++++++
drivers/event/dpaa2/dpaa2_eventdev.c | 74 ++++++++++++++++++++++
drivers/event/dpaa2/dpaa2_eventdev.h | 51 +++++++++++++++
.../event/dpaa2/rte_pmd_dpaa2_event_version.map | 3 +
mk/rte.app.mk | 1 +
8 files changed, 197 insertions(+)
create mode 100644 drivers/event/dpaa2/Makefile
create mode 100644 drivers/event/dpaa2/dpaa2_eventdev.c
create mode 100644 drivers/event/dpaa2/dpaa2_eventdev.h
create mode 100644 drivers/event/dpaa2/rte_pmd_dpaa2_event_version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index afb4cab..45e284e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -580,6 +580,10 @@ F: drivers/event/sw/
F: test/test/test_eventdev_sw.c
F: doc/guides/eventdevs/sw.rst
+NXP DPAA2 Eventdev PMD
+M: Hemant Agrawal <hemant.agrawal@nxp.com>
+M: Nipun Gupta <nipun.gupta@nxp.com>
+F: drivers/event/dpaa2/
Packet processing
-----------------
diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc
index 314a0ec..19fa2e2 100644
--- a/config/defconfig_arm64-dpaa2-linuxapp-gcc
+++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc
@@ -80,3 +80,9 @@ CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n
# on a single DPAA2 SEC device.
#
CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
+
+#
+# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
+#
+CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
+CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG=n
diff --git a/drivers/event/Makefile b/drivers/event/Makefile
index 1cf389e..0f12cc9 100644
--- a/drivers/event/Makefile
+++ b/drivers/event/Makefile
@@ -39,5 +39,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV) += sw
DEPDIRS-sw = $(core-libs) librte_kvargs librte_ring
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += octeontx
DEPDIRS-octeontx = $(core-libs)
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2
+DEPDIRS-dpaa2 = $(core-libs) librte_bus_fslmc
include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/event/dpaa2/Makefile b/drivers/event/dpaa2/Makefile
new file mode 100644
index 0000000..b76cf58
--- /dev/null
+++ b/drivers/event/dpaa2/Makefile
@@ -0,0 +1,56 @@
+# BSD LICENSE
+#
+# Copyright(c) 2017 NXP.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of NXP nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_pmd_dpaa2_event.a
+
+CFLAGS += $(WERROR_FLAGS)
+
+CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2
+# versioning export map
+EXPORT_MAP := rte_pmd_dpaa2_event_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_eventdev.c
+
+# this lib depends upon:
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += lib/librte_eventdev
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
new file mode 100644
index 0000000..191901e
--- /dev/null
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -0,0 +1,74 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of NXP nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rte_eal.h>
+#include <rte_vdev.h>
+
+#include "dpaa2_eventdev.h"
+
+static int
+dpaa2_eventdev_create(const char *name)
+{
+ RTE_SET_USED(name);
+
+ return 0;
+}
+
+static int
+dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
+{
+ const char *name;
+
+ name = rte_vdev_device_name(vdev);
+ PMD_DRV_LOG(INFO, PMD, "Initializing %s\n", name);
+ return dpaa2_eventdev_create(name);
+}
+
+static int
+dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
+{
+ const char *name;
+
+ name = rte_vdev_device_name(vdev);
+ PMD_DRV_LOG(INFO, "Closing %s", name);
+
+ RTE_SET_USED(name);
+
+ return 0;
+}
+
+static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
+ .probe = dpaa2_eventdev_probe,
+ .remove = dpaa2_eventdev_remove
+};
+
+RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h
new file mode 100644
index 0000000..959f443
--- /dev/null
+++ b/drivers/event/dpaa2/dpaa2_eventdev.h
@@ -0,0 +1,51 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of NXP nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DPAA2_EVENTDEV_H__
+#define __DPAA2_EVENTDEV_H__
+
+#include <rte_eventdev_pmd.h>
+#define EVENTDEV_NAME_DPAA2_PMD event_dpaa2
+
+#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG
+#define PMD_DRV_LOG(level, fmt, args...) \
+ RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#define PMD_DRV_FUNC_TRACE() PMD_DRV_LOG(DEBUG, ">>")
+#else
+#define PMD_DRV_LOG(level, fmt, args...) do { } while (0)
+#define PMD_DRV_FUNC_TRACE() do { } while (0)
+#endif
+
+#define PMD_DRV_ERR(fmt, args...) \
+ RTE_LOG(ERR, PMD, "%s(): " fmt "\n", __func__, ## args)
+
+#endif /* __DPAA2_EVENTDEV_H__ */
diff --git a/drivers/event/dpaa2/rte_pmd_dpaa2_event_version.map b/drivers/event/dpaa2/rte_pmd_dpaa2_event_version.map
new file mode 100644
index 0000000..1c0b755
--- /dev/null
+++ b/drivers/event/dpaa2/rte_pmd_dpaa2_event_version.map
@@ -0,0 +1,3 @@
+DPDK_17.08 {
+ local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index bcaf1b3..38990c0 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -171,6 +171,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_EVENTDEV),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV) += -lrte_pmd_skeleton_event
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV) += -lrte_pmd_sw_event
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += -lrte_pmd_octeontx_ssovf
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += -lrte_pmd_dpaa2_event
endif # CONFIG_RTE_LIBRTE_EVENTDEV
ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_PMD),y)
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 01/20] event/dpaa2: add basic build infrastructure
2017-05-25 18:07 ` [dpdk-dev] [PATCH 01/20] event/dpaa2: add basic build infrastructure Nipun Gupta
@ 2017-05-31 14:59 ` Jerin Jacob
0 siblings, 0 replies; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 14:59 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:32 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 01/20] event/dpaa2: add basic build infrastructure
> X-Mailer: git-send-email 1.9.1
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [dpdk-dev] [PATCH 02/20] bus/fslmc: generic framework for mc object creation
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 01/20] event/dpaa2: add basic build infrastructure Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 03/20] bus/fslmc: integrating dpio and dpbp to object framework Nipun Gupta
` (18 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
From: Hemant Agrawal <hemant.agrawal@nxp.com>
There are muliple help mc object, which are not an independent
device, but they are required for dpaa2 based devices.
This framework allows registration and handling of all such
mc devices.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 11 +++++++++
drivers/bus/fslmc/fslmc_vfio.h | 37 +++++++++++++++++++++++++++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 6 +++++
3 files changed, 54 insertions(+)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 5d4ac67..b9ea358 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -80,6 +80,17 @@
void *(*rte_mcp_ptr_list);
static uint32_t mcp_id;
static int is_dma_done;
+static struct rte_fslmc_object_list fslmc_obj_list =
+ TAILQ_HEAD_INITIALIZER(fslmc_obj_list);
+
+/*register a fslmc bus based dpaa2 driver */
+void
+rte_fslmc_object_register(struct rte_dpaa2_object *object)
+{
+ RTE_VERIFY(object);
+
+ TAILQ_INSERT_TAIL(&fslmc_obj_list, object, next);
+}
static int vfio_connect_container(struct fslmc_vfio_group *vfio_group)
{
diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h
index 53dd0b7..58b3acd 100644
--- a/drivers/bus/fslmc/fslmc_vfio.h
+++ b/drivers/bus/fslmc/fslmc_vfio.h
@@ -63,6 +63,24 @@
struct fslmc_vfio_group *group_list[VFIO_MAX_GRP];
} fslmc_vfio_container;
+struct rte_dpaa2_object;
+
+TAILQ_HEAD(rte_fslmc_object_list, rte_dpaa2_object);
+
+typedef int (*rte_fslmc_obj_create_t)(struct fslmc_vfio_device *vdev,
+ struct vfio_device_info *obj_info,
+ int object_id);
+
+/**
+ * A structure describing a DPAA2 driver.
+ */
+struct rte_dpaa2_object {
+ TAILQ_ENTRY(rte_dpaa2_object) next; /**< Next in list. */
+ const char *name; /**< Name of Object. */
+ uint16_t object_id; /**< DPAA2 Object ID */
+ rte_fslmc_obj_create_t create;
+};
+
int vfio_dmamap_mem_region(
uint64_t vaddr,
uint64_t iova,
@@ -79,4 +97,23 @@ int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
int dpaa2_create_dpbp_device(int dpbp_id);
+/**
+ * Register a DPAA2 MC Object driver.
+ *
+ * @param mc_object
+ * A pointer to a rte_dpaa_object structure describing the mc object
+ * to be registered.
+ */
+void rte_fslmc_object_register(struct rte_dpaa2_object *object);
+
+/** Helper for DPAA2 object registration */
+#define RTE_PMD_REGISTER_DPAA2_OBJECT(nm, dpaa2_obj) \
+RTE_INIT(dpaa2objinitfn_ ##nm); \
+static void dpaa2objinitfn_ ##nm(void) \
+{\
+ (dpaa2_obj).name = RTE_STR(nm);\
+ rte_fslmc_object_register(&dpaa2_obj); \
+} \
+RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
+
#endif /* _FSLMC_VFIO_H_ */
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 2db0fce..4c03e67 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -49,3 +49,9 @@ DPDK_17.05 {
local: *;
};
+
+DPDK_17.08 {
+ global:
+
+ rte_fslmc_object_register;
+} DPDK_17.05;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 03/20] bus/fslmc: integrating dpio and dpbp to object framework
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 01/20] event/dpaa2: add basic build infrastructure Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 02/20] bus/fslmc: generic framework for mc object creation Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 04/20] bus/fslmc: adding basic dpcon support Nipun Gupta
` (17 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
This patch removes the existing static call for dpio and dpbp
create and add them to object registration framework.
This patch also changes the vfio mc object processing to use
the framework.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 24 ++++++++++--------------
drivers/bus/fslmc/fslmc_vfio.h | 9 ++-------
drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c | 14 +++++++++++---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 11 +++++++++--
4 files changed, 32 insertions(+), 26 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index b9ea358..07a9278 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -377,7 +377,6 @@ int fslmc_vfio_process_group(void)
char path[PATH_MAX];
int64_t v_addr;
int ndev_count;
- int dpio_count = 0, dpbp_count = 0;
struct fslmc_vfio_group *group = &vfio_groups[0];
static int process_once;
@@ -520,18 +519,17 @@ int fslmc_vfio_process_group(void)
object_type, object_id);
fslmc_bus_add_device(dev);
- }
- if (!strcmp(object_type, "dpio")) {
- ret = dpaa2_create_dpio_device(vdev,
- &device_info,
+ } else {
+ /* Parse all other objects */
+ struct rte_dpaa2_object *object;
+
+ TAILQ_FOREACH(object, &fslmc_obj_list, next) {
+ if (!strcmp(object_type, object->name))
+ object->create(vdev, &device_info,
object_id);
- if (!ret)
- dpio_count++;
- }
- if (!strcmp(object_type, "dpbp")) {
- ret = dpaa2_create_dpbp_device(object_id);
- if (!ret)
- dpbp_count++;
+ else
+ continue;
+ }
}
}
closedir(d);
@@ -540,8 +538,6 @@ int fslmc_vfio_process_group(void)
if (ret)
FSLMC_VFIO_LOG(DEBUG, "Error in affining qbman swp %d", ret);
- FSLMC_VFIO_LOG(DEBUG, "DPAA2: Added dpbp_count = %d dpio_count=%d\n",
- dpbp_count, dpio_count);
return 0;
FAILURE:
diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h
index 58b3acd..ffed62e 100644
--- a/drivers/bus/fslmc/fslmc_vfio.h
+++ b/drivers/bus/fslmc/fslmc_vfio.h
@@ -39,6 +39,8 @@
#define DPAA2_VENDOR_ID 0x1957
#define DPAA2_MC_DPNI_DEVID 7
#define DPAA2_MC_DPSECI_DEVID 3
+#define DPAA2_MC_DPIO_DEVID 9
+#define DPAA2_MC_DPBP_DEVID 10
#define VFIO_MAX_GRP 1
@@ -90,13 +92,6 @@ int vfio_dmamap_mem_region(
int fslmc_vfio_process_group(void);
int rte_fslmc_vfio_dmamap(void);
-/* create dpio device */
-int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
- struct vfio_device_info *obj_info,
- int object_id);
-
-int dpaa2_create_dpbp_device(int dpbp_id);
-
/**
* Register a DPAA2 MC Object driver.
*
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
index 2fb285c..7575bf9 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
@@ -56,9 +56,10 @@
TAILQ_HEAD(dpbp_device_list, dpaa2_dpbp_dev);
static struct dpbp_device_list *dpbp_dev_list; /*!< DPBP device list */
-int
-dpaa2_create_dpbp_device(
- int dpbp_id)
+static int
+dpaa2_create_dpbp_device(struct fslmc_vfio_device *vdev __rte_unused,
+ struct vfio_device_info *obj_info __rte_unused,
+ int dpbp_id)
{
struct dpaa2_dpbp_dev *dpbp_node;
int ret;
@@ -137,3 +138,10 @@ void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp)
}
}
}
+
+static struct rte_dpaa2_object rte_dpaa2_dpbp_obj = {
+ .object_id = DPAA2_MC_DPBP_DEVID,
+ .create = dpaa2_create_dpbp_device,
+};
+
+RTE_PMD_REGISTER_DPAA2_OBJECT(dpbp, rte_dpaa2_dpbp_obj);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index a1a58b9..1dcc91f 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -320,10 +320,10 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
}
}
-int
+static int
dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
struct vfio_device_info *obj_info,
- int object_id)
+ int object_id)
{
struct dpaa2_dpio_dev *dpio_dev;
struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
@@ -443,3 +443,10 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
return -1;
}
+
+static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
+ .object_id = DPAA2_MC_DPIO_DEVID,
+ .create = dpaa2_create_dpio_device,
+};
+
+RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 04/20] bus/fslmc: adding basic dpcon support
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (2 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 03/20] bus/fslmc: integrating dpio and dpbp to object framework Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 05/20] bus/fslmc: export qbman dqrr funcs for eventdev usages Nipun Gupta
` (16 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/Makefile | 3 +-
drivers/bus/fslmc/fslmc_vfio.h | 1 +
drivers/bus/fslmc/mc/dpcon.c | 230 +++++++++++++++++++++++++++
drivers/bus/fslmc/mc/fsl_dpcon.h | 238 ++++++++++++++++++++++++++++
drivers/bus/fslmc/mc/fsl_dpcon_cmd.h | 175 ++++++++++++++++++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 +
6 files changed, 648 insertions(+), 1 deletion(-)
create mode 100644 drivers/bus/fslmc/mc/dpcon.c
create mode 100644 drivers/bus/fslmc/mc/fsl_dpcon.h
create mode 100644 drivers/bus/fslmc/mc/fsl_dpcon_cmd.h
diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile
index 973d279..7ef805b 100644
--- a/drivers/bus/fslmc/Makefile
+++ b/drivers/bus/fslmc/Makefile
@@ -65,7 +65,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \
mc/dpbp.c \
mc/dpio.c \
- mc/mc_sys.c
+ mc/mc_sys.c \
+ mc/dpcon.c \
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpbp.c
diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h
index ffed62e..eddce31 100644
--- a/drivers/bus/fslmc/fslmc_vfio.h
+++ b/drivers/bus/fslmc/fslmc_vfio.h
@@ -39,6 +39,7 @@
#define DPAA2_VENDOR_ID 0x1957
#define DPAA2_MC_DPNI_DEVID 7
#define DPAA2_MC_DPSECI_DEVID 3
+#define DPAA2_MC_DPCON_DEVID 5
#define DPAA2_MC_DPIO_DEVID 9
#define DPAA2_MC_DPBP_DEVID 10
diff --git a/drivers/bus/fslmc/mc/dpcon.c b/drivers/bus/fslmc/mc/dpcon.c
new file mode 100644
index 0000000..b078dff
--- /dev/null
+++ b/drivers/bus/fslmc/mc/dpcon.c
@@ -0,0 +1,230 @@
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fsl_mc_sys.h>
+#include <fsl_mc_cmd.h>
+#include <fsl_dpcon.h>
+#include <fsl_dpcon_cmd.h>
+
+int dpcon_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpcon_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPCON_CMD_OPEN(cmd, dpcon_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpcon_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpcon_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpcon_cfg *cfg,
+ uint32_t *obj_id)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CREATE,
+ cmd_flags,
+ dprc_token);
+ DPCON_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ CMD_CREATE_RSP_GET_OBJ_ID_PARAM0(cmd, *obj_id);
+
+ return 0;
+}
+
+int dpcon_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DESTROY,
+ cmd_flags,
+ dprc_token);
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id);
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpcon_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpcon_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpcon_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCON_RSP_IS_ENABLED(cmd, *en);
+
+ return 0;
+}
+
+int dpcon_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
+ cmd_flags, token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpcon_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpcon_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCON_RSP_GET_ATTR(cmd, attr);
+
+ return 0;
+}
+
+int dpcon_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
+ cmd_flags,
+ 0);
+
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPCON_RSP_GET_API_VERSION(cmd, *major_ver, *minor_ver);
+
+ return 0;
+}
diff --git a/drivers/bus/fslmc/mc/fsl_dpcon.h b/drivers/bus/fslmc/mc/fsl_dpcon.h
new file mode 100644
index 0000000..0ed9db5
--- /dev/null
+++ b/drivers/bus/fslmc/mc/fsl_dpcon.h
@@ -0,0 +1,238 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DPCON_H
+#define __FSL_DPCON_H
+
+/* Data Path Concentrator API
+ * Contains initialization APIs and runtime control APIs for DPCON
+ */
+
+struct fsl_mc_io;
+
+/** General DPCON macros */
+
+/**
+ * Use it to disable notifications; see dpcon_set_notification()
+ */
+#define DPCON_INVALID_DPIO_ID (int)(-1)
+
+/**
+ * dpcon_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpcon_id: DPCON unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpcon_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpcon_id,
+ uint16_t *token);
+
+/**
+ * dpcon_close() - Close the control session of the object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * struct dpcon_cfg - Structure representing DPCON configuration
+ * @num_priorities: Number of priorities for the DPCON channel (1-8)
+ */
+struct dpcon_cfg {
+ uint8_t num_priorities;
+};
+
+/**
+ * dpcon_create() - Create the DPCON object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @obj_id: returned object id
+ *
+ * Create the DPCON object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpcon_cfg *cfg,
+ uint32_t *obj_id);
+
+/**
+ * dpcon_destroy() - Destroy the DPCON object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id: The object id; it must be a valid id within the container that
+ * created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpcon_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id);
+
+/**
+ * dpcon_enable() - Enable the DPCON
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ *
+ * Return: '0' on Success; Error code otherwise
+ */
+int dpcon_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpcon_disable() - Disable the DPCON
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ *
+ * Return: '0' on Success; Error code otherwise
+ */
+int dpcon_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpcon_is_enabled() - Check if the DPCON is enabled.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ * @en: Returns '1' if object is enabled; '0' otherwise
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en);
+
+/**
+ * dpcon_reset() - Reset the DPCON, returns the object to initial state.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * struct dpcon_attr - Structure representing DPCON attributes
+ * @id: DPCON object ID
+ * @qbman_ch_id: Channel ID to be used by dequeue operation
+ * @num_priorities: Number of priorities for the DPCON channel (1-8)
+ */
+struct dpcon_attr {
+ int id;
+ uint16_t qbman_ch_id;
+ uint8_t num_priorities;
+};
+
+/**
+ * dpcon_get_attributes() - Retrieve DPCON attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCON object
+ * @attr: Object's attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpcon_attr *attr);
+
+/**
+ * dpcon_get_api_version() - Get Data Path Concentrator API version
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: Major version of data path concentrator API
+ * @minor_ver: Minor version of data path concentrator API
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpcon_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver);
+
+#endif /* __FSL_DPCON_H */
diff --git a/drivers/bus/fslmc/mc/fsl_dpcon_cmd.h b/drivers/bus/fslmc/mc/fsl_dpcon_cmd.h
new file mode 100644
index 0000000..f7f7690
--- /dev/null
+++ b/drivers/bus/fslmc/mc/fsl_dpcon_cmd.h
@@ -0,0 +1,175 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DPCON_CMD_H
+#define _FSL_DPCON_CMD_H
+
+/* DPCON Version */
+#define DPCON_VER_MAJOR 3
+#define DPCON_VER_MINOR 2
+
+/* Command IDs */
+#define DPCON_CMDID_CLOSE ((0x800 << 4) | (0x1))
+#define DPCON_CMDID_OPEN ((0x808 << 4) | (0x1))
+#define DPCON_CMDID_CREATE ((0x908 << 4) | (0x1))
+#define DPCON_CMDID_DESTROY ((0x988 << 4) | (0x1))
+#define DPCON_CMDID_GET_API_VERSION ((0xa08 << 4) | (0x1))
+
+#define DPCON_CMDID_ENABLE ((0x002 << 4) | (0x1))
+#define DPCON_CMDID_DISABLE ((0x003 << 4) | (0x1))
+#define DPCON_CMDID_GET_ATTR ((0x004 << 4) | (0x1))
+#define DPCON_CMDID_RESET ((0x005 << 4) | (0x1))
+#define DPCON_CMDID_IS_ENABLED ((0x006 << 4) | (0x1))
+
+#define DPCON_CMDID_SET_IRQ ((0x010 << 4) | (0x1))
+#define DPCON_CMDID_GET_IRQ ((0x011 << 4) | (0x1))
+#define DPCON_CMDID_SET_IRQ_ENABLE ((0x012 << 4) | (0x1))
+#define DPCON_CMDID_GET_IRQ_ENABLE ((0x013 << 4) | (0x1))
+#define DPCON_CMDID_SET_IRQ_MASK ((0x014 << 4) | (0x1))
+#define DPCON_CMDID_GET_IRQ_MASK ((0x015 << 4) | (0x1))
+#define DPCON_CMDID_GET_IRQ_STATUS ((0x016 << 4) | (0x1))
+#define DPCON_CMDID_CLEAR_IRQ_STATUS ((0x017 << 4) | (0x1))
+
+#define DPCON_CMDID_SET_NOTIFICATION ((0x100 << 4) | (0x1))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_OPEN(cmd, dpcon_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_CREATE(cmd, cfg) \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_priorities)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_IS_ENABLED(cmd, en) \
+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_GET_IRQ(cmd, irq_index) \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_IRQ(cmd, type, irq_cfg) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val);\
+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
+ MC_RSP_OP(cmd, 2, 32, 32, int, type);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_IRQ_ENABLE(cmd, en) \
+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_GET_IRQ_MASK(cmd, irq_index) \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_IRQ_MASK(cmd, mask) \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_IRQ_STATUS(cmd, status) \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_ATTR(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_ch_id);\
+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_CMD_SET_NOTIFICATION(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dpio_id);\
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priority);\
+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCON_RSP_GET_API_VERSION(cmd, major, minor) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
+} while (0)
+
+#endif /* _FSL_DPCON_CMD_H */
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 4c03e67..92a7342 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -53,5 +53,7 @@ DPDK_17.05 {
DPDK_17.08 {
global:
+ dpcon_open;
+ dpcon_get_attributes;
rte_fslmc_object_register;
} DPDK_17.05;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 05/20] bus/fslmc: export qbman dqrr funcs for eventdev usages
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (3 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 04/20] bus/fslmc: adding basic dpcon support Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 06/20] event/dpaa2: register dpcon as dpaa2 device for bus scan Nipun Gupta
` (15 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
From: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/rte_bus_fslmc_version.map | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 92a7342..008aaa0 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -55,5 +55,13 @@ DPDK_17.08 {
dpcon_open;
dpcon_get_attributes;
+ qbman_eq_desc_set_dca;
+ qbman_get_dqrr_from_idx;
+ qbman_get_dqrr_idx;
+ qbman_result_DQ_fqd_ctx;
+ qbman_swp_dqrr_consume;
+ qbman_swp_dqrr_next;
+ qbman_swp_push_set;
+ rte_dpaa2_alloc_dpci_dev;
rte_fslmc_object_register;
} DPDK_17.05;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 06/20] event/dpaa2: register dpcon as dpaa2 device for bus scan
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (4 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 05/20] bus/fslmc: export qbman dqrr funcs for eventdev usages Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 07/20] bus/fslmc: adding basic dpci support Nipun Gupta
` (14 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Registering dpcon as dpaa2 type device handling initialization,
allocation and freeing of the device
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/event/dpaa2/Makefile | 8 ++
drivers/event/dpaa2/dpaa2_eventdev.h | 18 +++++
drivers/event/dpaa2/dpaa2_hw_dpcon.c | 139 +++++++++++++++++++++++++++++++++++
3 files changed, 165 insertions(+)
create mode 100644 drivers/event/dpaa2/dpaa2_hw_dpcon.c
diff --git a/drivers/event/dpaa2/Makefile b/drivers/event/dpaa2/Makefile
index b76cf58..001904a 100644
--- a/drivers/event/dpaa2/Makefile
+++ b/drivers/event/dpaa2/Makefile
@@ -38,7 +38,14 @@ LIB = librte_pmd_dpaa2_event.a
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc
+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include
+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc
+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2
CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2
+CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
+
# versioning export map
EXPORT_MAP := rte_pmd_dpaa2_event_version.map
@@ -47,6 +54,7 @@ LIBABIVER := 1
#
# all source are stored in SRCS-y
#
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_hw_dpcon.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_eventdev.c
# this lib depends upon:
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h
index 959f443..b151502 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.h
+++ b/drivers/event/dpaa2/dpaa2_eventdev.h
@@ -34,6 +34,10 @@
#define __DPAA2_EVENTDEV_H__
#include <rte_eventdev_pmd.h>
+#include <rte_atomic.h>
+#include <mc/fsl_dpcon.h>
+#include <mc/fsl_mc_sys.h>
+
#define EVENTDEV_NAME_DPAA2_PMD event_dpaa2
#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG
@@ -48,4 +52,18 @@
#define PMD_DRV_ERR(fmt, args...) \
RTE_LOG(ERR, PMD, "%s(): " fmt "\n", __func__, ## args)
+struct dpaa2_dpcon_dev {
+ TAILQ_ENTRY(dpaa2_dpcon_dev) next;
+ struct fsl_mc_io dpcon;
+ uint16_t token;
+ rte_atomic16_t in_use;
+ uint32_t dpcon_id;
+ uint16_t qbman_ch_id;
+ uint8_t num_priorities;
+ uint8_t channel_index;
+};
+
+struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
+void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
+
#endif /* __DPAA2_EVENTDEV_H__ */
diff --git a/drivers/event/dpaa2/dpaa2_hw_dpcon.c b/drivers/event/dpaa2/dpaa2_hw_dpcon.c
new file mode 100644
index 0000000..27f5bcb
--- /dev/null
+++ b/drivers/event/dpaa2/dpaa2_hw_dpcon.c
@@ -0,0 +1,139 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of NXP nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_string_fns.h>
+#include <rte_cycles.h>
+#include <rte_kvargs.h>
+#include <rte_dev.h>
+#include <rte_ethdev.h>
+
+#include <fslmc_vfio.h>
+#include <mc/fsl_dpcon.h>
+#include <portal/dpaa2_hw_pvt.h>
+#include "dpaa2_eventdev.h"
+
+TAILQ_HEAD(dpcon_dev_list, dpaa2_dpcon_dev);
+static struct dpcon_dev_list dpcon_dev_list
+ = TAILQ_HEAD_INITIALIZER(dpcon_dev_list); /*!< DPCON device list */
+
+static int
+rte_dpaa2_create_dpcon_device(struct fslmc_vfio_device *vdev __rte_unused,
+ struct vfio_device_info *obj_info __rte_unused,
+ int dpcon_id)
+{
+ struct dpaa2_dpcon_dev *dpcon_node;
+ struct dpcon_attr attr;
+ int ret;
+
+ /* Allocate DPAA2 dpcon handle */
+ dpcon_node = rte_malloc(NULL, sizeof(struct dpaa2_dpcon_dev), 0);
+ if (!dpcon_node) {
+ PMD_DRV_LOG(ERR, "Memory allocation failed for DPCON Device");
+ return -1;
+ }
+
+ /* Open the dpcon object */
+ dpcon_node->dpcon.regs = rte_mcp_ptr_list[MC_PORTAL_INDEX];
+ ret = dpcon_open(&dpcon_node->dpcon,
+ CMD_PRI_LOW, dpcon_id, &dpcon_node->token);
+ if (ret) {
+ PMD_DRV_LOG(ERR, "Resource alloc failure with err code: %d",
+ ret);
+ rte_free(dpcon_node);
+ return -1;
+ }
+
+ /* Get the device attributes */
+ ret = dpcon_get_attributes(&dpcon_node->dpcon,
+ CMD_PRI_LOW, dpcon_node->token, &attr);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Reading device failed with err code: %d",
+ ret);
+ rte_free(dpcon_node);
+ return -1;
+ }
+
+ /* Updating device specific private information*/
+ dpcon_node->qbman_ch_id = attr.qbman_ch_id;
+ dpcon_node->num_priorities = attr.num_priorities;
+ dpcon_node->dpcon_id = dpcon_id;
+ rte_atomic16_init(&dpcon_node->in_use);
+
+ TAILQ_INSERT_TAIL(&dpcon_dev_list, dpcon_node, next);
+
+ PMD_DRV_LOG(DEBUG, "DPAA2: Added [dpcon-%d]", dpcon_id);
+
+ return 0;
+}
+
+struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void)
+{
+ struct dpaa2_dpcon_dev *dpcon_dev = NULL;
+
+ /* Get DPCON dev handle from list using index */
+ TAILQ_FOREACH(dpcon_dev, &dpcon_dev_list, next) {
+ if (dpcon_dev && rte_atomic16_test_and_set(&dpcon_dev->in_use))
+ break;
+ }
+
+ return dpcon_dev;
+}
+
+void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon)
+{
+ struct dpaa2_dpcon_dev *dpcon_dev = NULL;
+
+ /* Match DPCON handle and mark it free */
+ TAILQ_FOREACH(dpcon_dev, &dpcon_dev_list, next) {
+ if (dpcon_dev == dpcon) {
+ rte_atomic16_dec(&dpcon_dev->in_use);
+ return;
+ }
+ }
+}
+
+static struct rte_dpaa2_object rte_dpaa2_dpcon_obj = {
+ .object_id = DPAA2_MC_DPCON_DEVID,
+ .create = rte_dpaa2_create_dpcon_device,
+};
+
+RTE_PMD_REGISTER_DPAA2_OBJECT(dpcon, rte_dpaa2_dpcon_obj);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 07/20] bus/fslmc: adding basic dpci support
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (5 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 06/20] event/dpaa2: register dpcon as dpaa2 device for bus scan Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 08/20] bus/fslmc: register dpci as dpaa2 device for bus scan Nipun Gupta
` (13 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/Makefile | 1 +
drivers/bus/fslmc/mc/dpci.c | 307 +++++++++++++++++++++
drivers/bus/fslmc/mc/fsl_dpci.h | 404 ++++++++++++++++++++++++++++
drivers/bus/fslmc/mc/fsl_dpci_cmd.h | 147 ++++++++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 1 +
5 files changed, 860 insertions(+)
create mode 100644 drivers/bus/fslmc/mc/dpci.c
create mode 100644 drivers/bus/fslmc/mc/fsl_dpci.h
create mode 100644 drivers/bus/fslmc/mc/fsl_dpci_cmd.h
diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile
index 7ef805b..f0ad576 100644
--- a/drivers/bus/fslmc/Makefile
+++ b/drivers/bus/fslmc/Makefile
@@ -67,6 +67,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \
mc/dpio.c \
mc/mc_sys.c \
mc/dpcon.c \
+ mc/dpci.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpbp.c
diff --git a/drivers/bus/fslmc/mc/dpci.c b/drivers/bus/fslmc/mc/dpci.c
new file mode 100644
index 0000000..0ea7837
--- /dev/null
+++ b/drivers/bus/fslmc/mc/dpci.c
@@ -0,0 +1,307 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fsl_mc_sys.h>
+#include <fsl_mc_cmd.h>
+#include <fsl_dpci.h>
+#include <fsl_dpci_cmd.h>
+
+int dpci_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpci_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPCI_CMD_OPEN(cmd, dpci_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpci_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_CLOSE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpci_cfg *cfg,
+ uint32_t *obj_id)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_CREATE,
+ cmd_flags,
+ dprc_token);
+ DPCI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ CMD_CREATE_RSP_GET_OBJ_ID_PARAM0(cmd, *obj_id);
+
+ return 0;
+}
+
+int dpci_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_DESTROY,
+ cmd_flags,
+ dprc_token);
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id);
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_ENABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_DISABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_IS_ENABLED, cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCI_RSP_IS_ENABLED(cmd, *en);
+
+ return 0;
+}
+
+int dpci_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_RESET,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpci_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_ATTR,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCI_RSP_GET_ATTRIBUTES(cmd, attr);
+
+ return 0;
+}
+
+int dpci_set_rx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ const struct dpci_rx_queue_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_SET_RX_QUEUE,
+ cmd_flags,
+ token);
+ DPCI_CMD_SET_RX_QUEUE(cmd, priority, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpci_get_rx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ struct dpci_rx_queue_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_RX_QUEUE,
+ cmd_flags,
+ token);
+ DPCI_CMD_GET_RX_QUEUE(cmd, priority);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCI_RSP_GET_RX_QUEUE(cmd, attr);
+
+ return 0;
+}
+
+int dpci_get_tx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ struct dpci_tx_queue_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_TX_QUEUE,
+ cmd_flags,
+ token);
+ DPCI_CMD_GET_TX_QUEUE(cmd, priority);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPCI_RSP_GET_TX_QUEUE(cmd, attr);
+
+ return 0;
+}
+
+int dpci_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_API_VERSION,
+ cmd_flags,
+ 0);
+
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPCI_RSP_GET_API_VERSION(cmd, *major_ver, *minor_ver);
+
+ return 0;
+}
diff --git a/drivers/bus/fslmc/mc/fsl_dpci.h b/drivers/bus/fslmc/mc/fsl_dpci.h
new file mode 100644
index 0000000..1e155dd
--- /dev/null
+++ b/drivers/bus/fslmc/mc/fsl_dpci.h
@@ -0,0 +1,404 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DPCI_H
+#define __FSL_DPCI_H
+
+/* Data Path Communication Interface API
+ * Contains initialization APIs and runtime control APIs for DPCI
+ */
+
+struct fsl_mc_io;
+
+/** General DPCI macros */
+
+/**
+ * Maximum number of Tx/Rx priorities per DPCI object
+ */
+#define DPCI_PRIO_NUM 2
+
+/**
+ * Indicates an invalid frame queue
+ */
+#define DPCI_FQID_NOT_VALID (uint32_t)(-1)
+
+/**
+ * All queues considered; see dpci_set_rx_queue()
+ */
+#define DPCI_ALL_QUEUES (uint8_t)(-1)
+
+/**
+ * dpci_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpci_id: DPCI unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpci_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpci_id,
+ uint16_t *token);
+
+/**
+ * dpci_close() - Close the control session of the object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * Enable the Order Restoration support
+ */
+#define DPCI_OPT_HAS_OPR 0x000040
+
+/**
+ * Order Point Records are shared for the entire DPCI
+ */
+#define DPCI_OPT_OPR_SHARED 0x000080
+
+/**
+ * struct dpci_cfg - Structure representing DPCI configuration
+ * @options: Any combination of the following options:
+ * DPCI_OPT_HAS_OPR
+ * DPCI_OPT_OPR_SHARED
+ * @num_of_priorities: Number of receive priorities (queues) for the DPCI;
+ * note, that the number of transmit priorities (queues)
+ * is determined by the number of receive priorities of
+ * the peer DPCI object
+ */
+struct dpci_cfg {
+ uint32_t options;
+ uint8_t num_of_priorities;
+};
+
+/**
+ * dpci_create() - Create the DPCI object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @obj_id: returned object id
+ *
+ * Create the DPCI object, allocate required resources and perform required
+ * initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpci_cfg *cfg,
+ uint32_t *obj_id);
+
+/**
+ * dpci_destroy() - Destroy the DPCI object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id: The object id; it must be a valid id within the container that
+ * created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpci_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id);
+
+/**
+ * dpci_enable() - Enable the DPCI, allow sending and receiving frames.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpci_disable() - Disable the DPCI, stop sending and receiving frames.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpci_is_enabled() - Check if the DPCI is enabled.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ * @en: Returns '1' if object is enabled; '0' otherwise
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en);
+
+/**
+ * dpci_reset() - Reset the DPCI, returns the object to initial state.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * struct dpci_attr - Structure representing DPCI attributes
+ * @id: DPCI object ID
+ * @num_of_priorities: Number of receive priorities
+ */
+struct dpci_attr {
+ int id;
+ uint8_t num_of_priorities;
+};
+
+/**
+ * dpci_get_attributes() - Retrieve DPCI attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ * @attr: Returned object's attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpci_attr *attr);
+
+/**
+ * enum dpci_dest - DPCI destination types
+ * @DPCI_DEST_NONE: Unassigned destination; The queue is set in parked mode
+ * and does not generate FQDAN notifications; user is
+ * expected to dequeue from the queue based on polling or
+ * other user-defined method
+ * @DPCI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
+ * notifications to the specified DPIO; user is expected
+ * to dequeue from the queue only after notification is
+ * received
+ * @DPCI_DEST_DPCON: The queue is set in schedule mode and does not generate
+ * FQDAN notifications, but is connected to the specified
+ * DPCON object;
+ * user is expected to dequeue from the DPCON channel
+ */
+enum dpci_dest {
+ DPCI_DEST_NONE = 0,
+ DPCI_DEST_DPIO = 1,
+ DPCI_DEST_DPCON = 2
+};
+
+/**
+ * struct dpci_dest_cfg - Structure representing DPCI destination configuration
+ * @dest_type: Destination type
+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
+ * @priority: Priority selection within the DPIO or DPCON channel; valid
+ * values are 0-1 or 0-7, depending on the number of priorities
+ * in that channel; not relevant for 'DPCI_DEST_NONE' option
+ */
+struct dpci_dest_cfg {
+ enum dpci_dest dest_type;
+ int dest_id;
+ uint8_t priority;
+};
+
+/** DPCI queue modification options */
+
+/**
+ * Select to modify the user's context associated with the queue
+ */
+#define DPCI_QUEUE_OPT_USER_CTX 0x00000001
+
+/**
+ * Select to modify the queue's destination
+ */
+#define DPCI_QUEUE_OPT_DEST 0x00000002
+
+/**
+ * struct dpci_rx_queue_cfg - Structure representing RX queue configuration
+ * @options: Flags representing the suggested modifications to the queue;
+ * Use any combination of 'DPCI_QUEUE_OPT_<X>' flags
+ * @user_ctx: User context value provided in the frame descriptor of each
+ * dequeued frame;
+ * valid only if 'DPCI_QUEUE_OPT_USER_CTX' is contained in
+ * 'options'
+ * @dest_cfg: Queue destination parameters;
+ * valid only if 'DPCI_QUEUE_OPT_DEST' is contained in 'options'
+ */
+struct dpci_rx_queue_cfg {
+ uint32_t options;
+ uint64_t user_ctx;
+ struct dpci_dest_cfg dest_cfg;
+};
+
+/**
+ * dpci_set_rx_queue() - Set Rx queue configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ * @priority: Select the queue relative to number of
+ * priorities configured at DPCI creation; use
+ * DPCI_ALL_QUEUES to configure all Rx queues
+ * identically.
+ * @cfg: Rx queue configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_set_rx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ const struct dpci_rx_queue_cfg *cfg);
+
+/**
+ * struct dpci_rx_queue_attr - Structure representing Rx queue attributes
+ * @user_ctx: User context value provided in the frame descriptor of each
+ * dequeued frame
+ * @dest_cfg: Queue destination configuration
+ * @fqid: Virtual FQID value to be used for dequeue operations
+ */
+struct dpci_rx_queue_attr {
+ uint64_t user_ctx;
+ struct dpci_dest_cfg dest_cfg;
+ uint32_t fqid;
+};
+
+/**
+ * dpci_get_rx_queue() - Retrieve Rx queue attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ * @priority: Select the queue relative to number of
+ * priorities configured at DPCI creation
+ * @attr: Returned Rx queue attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_get_rx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ struct dpci_rx_queue_attr *attr);
+
+/**
+ * struct dpci_tx_queue_attr - Structure representing attributes of Tx queues
+ * @fqid: Virtual FQID to be used for sending frames to peer DPCI;
+ * returns 'DPCI_FQID_NOT_VALID' if a no peer is connected or if
+ * the selected priority exceeds the number of priorities of the
+ * peer DPCI object
+ */
+struct dpci_tx_queue_attr {
+ uint32_t fqid;
+};
+
+/**
+ * dpci_get_tx_queue() - Retrieve Tx queue attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPCI object
+ * @priority: Select the queue relative to number of
+ * priorities of the peer DPCI object
+ * @attr: Returned Tx queue attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_get_tx_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t priority,
+ struct dpci_tx_queue_attr *attr);
+
+/**
+ * dpci_get_api_version() - Get communication interface API version
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: Major version of data path communication interface API
+ * @minor_ver: Minor version of data path communication interface API
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpci_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver);
+
+#endif /* __FSL_DPCI_H */
diff --git a/drivers/bus/fslmc/mc/fsl_dpci_cmd.h b/drivers/bus/fslmc/mc/fsl_dpci_cmd.h
new file mode 100644
index 0000000..6d4e273
--- /dev/null
+++ b/drivers/bus/fslmc/mc/fsl_dpci_cmd.h
@@ -0,0 +1,147 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DPCI_CMD_H
+#define _FSL_DPCI_CMD_H
+
+/* DPCI Version */
+#define DPCI_VER_MAJOR 3
+#define DPCI_VER_MINOR 3
+
+/* Command IDs */
+#define DPCI_CMDID_CLOSE 0x8001
+#define DPCI_CMDID_OPEN 0x8071
+#define DPCI_CMDID_CREATE 0x9072
+#define DPCI_CMDID_DESTROY 0x9871
+#define DPCI_CMDID_GET_API_VERSION 0xa071
+
+#define DPCI_CMDID_ENABLE 0x0021
+#define DPCI_CMDID_DISABLE 0x0031
+#define DPCI_CMDID_GET_ATTR 0x0041
+#define DPCI_CMDID_RESET 0x0051
+#define DPCI_CMDID_IS_ENABLED 0x0061
+
+#define DPCI_CMDID_SET_IRQ_ENABLE 0x0121
+#define DPCI_CMDID_GET_IRQ_ENABLE 0x0131
+#define DPCI_CMDID_SET_IRQ_MASK 0x0141
+#define DPCI_CMDID_GET_IRQ_MASK 0x0151
+#define DPCI_CMDID_GET_IRQ_STATUS 0x0161
+#define DPCI_CMDID_CLEAR_IRQ_STATUS 0x0171
+
+#define DPCI_CMDID_SET_RX_QUEUE 0x0e01
+#define DPCI_CMDID_GET_LINK_STATE 0x0e11
+#define DPCI_CMDID_GET_PEER_ATTR 0x0e21
+#define DPCI_CMDID_GET_RX_QUEUE 0x0e31
+#define DPCI_CMDID_GET_TX_QUEUE 0x0e41
+#define DPCI_CMDID_SET_OPR 0x0e51
+#define DPCI_CMDID_GET_OPR 0x0e61
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_CMD_OPEN(cmd, dpci_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, dpci_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_of_priorities);\
+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_IS_ENABLED(cmd, en) \
+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, (attr)->id);\
+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, (attr)->num_of_priorities);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_PEER_ATTR(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->peer_id);\
+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_of_priorities);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_LINK_STATE(cmd, up) \
+ MC_RSP_OP(cmd, 0, 0, 1, int, up)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_CMD_SET_RX_QUEUE(cmd, priority, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id);\
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority);\
+ MC_CMD_OP(cmd, 0, 48, 4, enum dpci_dest, cfg->dest_cfg.dest_type);\
+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\
+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_CMD_GET_RX_QUEUE(cmd, priority) \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_RX_QUEUE(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
+ MC_RSP_OP(cmd, 0, 48, 4, enum dpci_dest, attr->dest_cfg.dest_type);\
+ MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_CMD_GET_TX_QUEUE(cmd, priority) \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_TX_QUEUE(cmd, attr) \
+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPCI_RSP_GET_API_VERSION(cmd, major, minor) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
+} while (0)
+
+#endif /* _FSL_DPCI_CMD_H */
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 008aaa0..4f62e08 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -53,6 +53,7 @@ DPDK_17.05 {
DPDK_17.08 {
global:
+ dpci_set_rx_queue;
dpcon_open;
dpcon_get_attributes;
qbman_eq_desc_set_dca;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 08/20] bus/fslmc: register dpci as dpaa2 device for bus scan
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (6 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 07/20] bus/fslmc: adding basic dpci support Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 09/20] bus/fslmc: adding cpu support in stashing config Nipun Gupta
` (12 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Registering dpci as dpaa2 type device handling initialization,
allocation and freeing of the device
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/Makefile | 1 +
drivers/bus/fslmc/fslmc_vfio.h | 1 +
drivers/bus/fslmc/portal/dpaa2_hw_dpci.c | 179 +++++++++++++++++++++++++++++++
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 15 +++
4 files changed, 196 insertions(+)
create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile
index f0ad576..364c214 100644
--- a/drivers/bus/fslmc/Makefile
+++ b/drivers/bus/fslmc/Makefile
@@ -71,6 +71,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpbp.c
+SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpci.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_vfio.c
SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_bus.c
diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h
index eddce31..7c725f4 100644
--- a/drivers/bus/fslmc/fslmc_vfio.h
+++ b/drivers/bus/fslmc/fslmc_vfio.h
@@ -42,6 +42,7 @@
#define DPAA2_MC_DPCON_DEVID 5
#define DPAA2_MC_DPIO_DEVID 9
#define DPAA2_MC_DPBP_DEVID 10
+#define DPAA2_MC_DPCI_DEVID 11
#define VFIO_MAX_GRP 1
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
new file mode 100644
index 0000000..d222f26
--- /dev/null
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
@@ -0,0 +1,179 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_string_fns.h>
+#include <rte_cycles.h>
+#include <rte_kvargs.h>
+#include <rte_dev.h>
+#include <rte_ethdev.h>
+
+#include <fslmc_logs.h>
+#include <fslmc_vfio.h>
+#include <mc/fsl_dpci.h>
+#include "portal/dpaa2_hw_pvt.h"
+#include "portal/dpaa2_hw_dpio.h"
+
+TAILQ_HEAD(dpci_dev_list, dpaa2_dpci_dev);
+static struct dpci_dev_list dpci_dev_list
+ = TAILQ_HEAD_INITIALIZER(dpci_dev_list); /*!< DPCI device list */
+
+static int
+rte_dpaa2_create_dpci_device(struct fslmc_vfio_device *vdev __rte_unused,
+ struct vfio_device_info *obj_info __rte_unused,
+ int dpci_id)
+{
+ struct dpaa2_dpci_dev *dpci_node;
+ struct dpci_attr attr;
+ struct dpci_rx_queue_cfg rx_queue_cfg;
+ struct dpci_rx_queue_attr rx_attr;
+ int ret, i;
+
+ /* Allocate DPAA2 dpci handle */
+ dpci_node = rte_malloc(NULL, sizeof(struct dpaa2_dpci_dev), 0);
+ if (!dpci_node) {
+ PMD_INIT_LOG(ERR, "Memory allocation failed for DPCI Device");
+ return -1;
+ }
+
+ /* Open the dpci object */
+ dpci_node->dpci.regs = rte_mcp_ptr_list[MC_PORTAL_INDEX];
+ ret = dpci_open(&dpci_node->dpci,
+ CMD_PRI_LOW, dpci_id, &dpci_node->token);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Resource alloc failure with err code: %d",
+ ret);
+ rte_free(dpci_node);
+ return -1;
+ }
+
+ /* Get the device attributes */
+ ret = dpci_get_attributes(&dpci_node->dpci,
+ CMD_PRI_LOW, dpci_node->token, &attr);
+ if (ret != 0) {
+ PMD_INIT_LOG(ERR, "Reading device failed with err code: %d",
+ ret);
+ rte_free(dpci_node);
+ return -1;
+ }
+
+ /* Set up the Rx Queue */
+ memset(&rx_queue_cfg, 0, sizeof(struct dpci_rx_queue_cfg));
+ ret = dpci_set_rx_queue(&dpci_node->dpci,
+ CMD_PRI_LOW,
+ dpci_node->token,
+ 0, &rx_queue_cfg);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Setting Rx queue failed with err code: %d",
+ ret);
+ rte_free(dpci_node);
+ return -1;
+ }
+
+ /* Enable the device */
+ ret = dpci_enable(&dpci_node->dpci,
+ CMD_PRI_LOW, dpci_node->token);
+ if (ret != 0) {
+ PMD_INIT_LOG(ERR, "Enabling device failed with err code: %d",
+ ret);
+ rte_free(dpci_node);
+ return -1;
+ }
+
+ for (i = 0; i < DPAA2_DPCI_MAX_QUEUES; i++) {
+ /* Get the Rx FQID's */
+ ret = dpci_get_rx_queue(&dpci_node->dpci,
+ CMD_PRI_LOW,
+ dpci_node->token, i,
+ &rx_attr);
+ if (ret != 0) {
+ PMD_INIT_LOG(ERR,
+ "Reading device failed with err code: %d",
+ ret);
+ rte_free(dpci_node);
+ return -1;
+ }
+
+ dpci_node->queue[i].fqid = rx_attr.fqid;
+ }
+
+ dpci_node->dpci_id = dpci_id;
+ rte_atomic16_init(&dpci_node->in_use);
+
+ TAILQ_INSERT_TAIL(&dpci_dev_list, dpci_node, next);
+
+ PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpci-%d]", dpci_id);
+
+ return 0;
+}
+
+struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void)
+{
+ struct dpaa2_dpci_dev *dpci_dev = NULL;
+
+ /* Get DPCI dev handle from list using index */
+ TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) {
+ if (dpci_dev && rte_atomic16_test_and_set(&dpci_dev->in_use))
+ break;
+ }
+
+ return dpci_dev;
+}
+
+void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci)
+{
+ struct dpaa2_dpci_dev *dpci_dev = NULL;
+
+ /* Match DPCI handle and mark it free */
+ TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) {
+ if (dpci_dev == dpci) {
+ rte_atomic16_dec(&dpci_dev->in_use);
+ return;
+ }
+ }
+}
+
+static struct rte_dpaa2_object rte_dpaa2_dpci_obj = {
+ .object_id = DPAA2_MC_DPCI_DEVID,
+ .create = rte_dpaa2_create_dpci_device,
+};
+
+RTE_PMD_REGISTER_DPAA2_OBJECT(dpci, rte_dpaa2_dpci_obj);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index c022373..9f9df50 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -75,6 +75,8 @@
#define DPAA2_HW_BUF_RESERVE 0
#define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
+#define DPAA2_DPCI_MAX_QUEUES 2
+
struct dpaa2_dpio_dev {
TAILQ_ENTRY(dpaa2_dpio_dev) next;
/**< Pointer to Next device instance */
@@ -123,6 +125,16 @@ struct dpaa2_queue {
struct queue_storage_info_t *q_storage;
};
+struct dpaa2_dpci_dev {
+ TAILQ_ENTRY(dpaa2_dpci_dev) next;
+ /**< Pointer to Next device instance */
+ struct fsl_mc_io dpci; /** handle to DPCI portal object */
+ uint16_t token;
+ rte_atomic16_t in_use;
+ uint32_t dpci_id; /*HW ID for DPCI object */
+ struct dpaa2_queue queue[DPAA2_DPCI_MAX_QUEUES];
+};
+
/*! Global MCP list */
extern void *(*rte_mcp_ptr_list);
@@ -267,4 +279,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
+struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
+void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);
+
#endif
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 09/20] bus/fslmc: adding cpu support in stashing config
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (7 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 08/20] bus/fslmc: register dpci as dpaa2 device for bus scan Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device Nipun Gupta
` (11 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Stashing can also be configured by other drivers (for instance
event driver) passing cpu_id as an argument. This change
facilitates the same.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 14 ++++++--------
drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 4 ++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 ++
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index 1dcc91f..f88d490 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -172,13 +172,11 @@
}
static int
-dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
+dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
{
- int sdest;
- int cpu_id, ret;
+ int sdest, ret;
/* Set the Stashing Destination */
- cpu_id = rte_lcore_id();
if (cpu_id < 0) {
cpu_id = rte_get_master_lcore();
if (cpu_id < 0) {
@@ -206,7 +204,7 @@
return 0;
}
-static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
+struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
{
struct dpaa2_dpio_dev *dpio_dev = NULL;
int ret;
@@ -222,7 +220,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
dpio_dev, dpio_dev->index, syscall(SYS_gettid));
- ret = dpaa2_configure_stashing(dpio_dev);
+ ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
if (ret)
PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
@@ -262,7 +260,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
}
/* Populate the dpaa2_io_portal structure */
- dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();
+ dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
if (dpaa2_io_portal[lcore_id].dpio_dev) {
RTE_PER_LCORE(_dpaa2_io).dpio_dev
@@ -308,7 +306,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
}
/* Populate the dpaa2_io_portal structure */
- dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp();
+ dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
index f2e1168..4269800 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
@@ -53,6 +53,10 @@ struct dpaa2_io_portal_t {
#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal
+extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
+
+struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id);
+
/* Affine a DPIO portal to current processing thread */
int dpaa2_affine_qbman_swp(void);
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 4f62e08..fdc6e21 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -53,6 +53,8 @@ DPDK_17.05 {
DPDK_17.08 {
global:
+ dpaa2_io_portal;
+ dpaa2_get_qbman_swp;
dpci_set_rx_queue;
dpcon_open;
dpcon_get_attributes;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (8 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 09/20] bus/fslmc: adding cpu support in stashing config Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-31 15:10 ` Jerin Jacob
2017-05-25 18:07 ` [dpdk-dev] [PATCH 11/20] bus/fslmc: add support for static dequeue from portal Nipun Gupta
` (10 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/event/dpaa2/dpaa2_eventdev.c | 153 ++++++++++++++++++++++++++++++++++-
drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++++
2 files changed, 171 insertions(+), 4 deletions(-)
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index 191901e..7fa17f2 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -30,17 +30,164 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <assert.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdint.h>
+#include <sys/epoll.h>
+
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_debug.h>
+#include <rte_dev.h>
#include <rte_eal.h>
+#include <rte_log.h>
+#include <rte_memory.h>
+#include <rte_memzone.h>
+#include <rte_malloc.h>
+#include <rte_pci.h>
+#include <rte_lcore.h>
#include <rte_vdev.h>
+#include <rte_fslmc.h>
+#include <rte_atomic.h>
+#include <fslmc_vfio.h>
+#include <dpaa2_hw_pvt.h>
+#include <dpaa2_hw_mempool.h>
+#include <dpaa2_hw_dpio.h>
#include "dpaa2_eventdev.h"
+#include <portal/dpaa2_hw_pvt.h>
+#include <mc/fsl_dpci.h>
+
+/* Clarifications
+ * Evendev = SoC Instance
+ * Eventport = DPIO Instance
+ * Eventqueue = DPCON Instance
+ * 1 Eventdev can have N Eventqueue
+ * Soft Event Flow is DPCI Instance
+ */
+
+static uint16_t
+dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
+ uint16_t nb_events)
+{
+ RTE_SET_USED(port);
+ RTE_SET_USED(ev);
+ RTE_SET_USED(nb_events);
+
+ return 0;
+}
+
+static uint16_t
+dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
+{
+ return dpaa2_eventdev_enqueue_burst(port, ev, 1);
+}
+
+static uint16_t
+dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
+ uint16_t nb_events, uint64_t timeout_ticks)
+{
+ RTE_SET_USED(port);
+ RTE_SET_USED(ev);
+ RTE_SET_USED(nb_events);
+ RTE_SET_USED(timeout_ticks);
+
+ return 0;
+}
+
+static uint16_t
+dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
+ uint64_t timeout_ticks)
+{
+ return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
+}
+
+static const struct rte_eventdev_ops dpaa2_eventdev_ops;
+
+static int
+dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
+ struct dpaa2_dpcon_dev *dpcon_dev)
+{
+ struct dpci_rx_queue_cfg rx_queue_cfg;
+ int ret, i;
+
+ /*Do settings to get the frame on a DPCON object*/
+ rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST;
+ rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
+ rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
+ rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
+
+ for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
+ rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
+ ret = dpci_set_rx_queue(&dpci_dev->dpci,
+ CMD_PRI_LOW,
+ dpci_dev->token, i,
+ &rx_queue_cfg);
+ if (ret) {
+ PMD_DRV_LOG(ERR, PMD,
+ "set_rx_q failed with err code: %d", ret);
+ return ret;
+ }
+ }
+ return 0;
+}
static int
dpaa2_eventdev_create(const char *name)
{
- RTE_SET_USED(name);
+ struct rte_eventdev *eventdev;
+ struct dpaa2_eventdev *priv;
+ struct dpaa2_dpcon_dev *dpcon_dev = NULL;
+ struct dpaa2_dpci_dev *dpci_dev = NULL;
+ int ret;
+
+ eventdev = rte_event_pmd_vdev_init(name,
+ sizeof(struct dpaa2_eventdev),
+ rte_socket_id());
+ if (eventdev == NULL) {
+ PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
+ goto fail;
+ }
+
+ eventdev->dev_ops = &dpaa2_eventdev_ops;
+ eventdev->schedule = NULL;
+ eventdev->enqueue = dpaa2_eventdev_enqueue;
+ eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
+ eventdev->dequeue = dpaa2_eventdev_dequeue;
+ eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
+
+ priv = eventdev->data->dev_private;
+ priv->max_event_queues = 0;
+
+ do {
+ dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
+ if (!dpcon_dev)
+ break;
+ priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
+
+ dpci_dev = rte_dpaa2_alloc_dpci_dev();
+ if (!dpci_dev) {
+ rte_dpaa2_free_dpcon_dev(dpcon_dev);
+ break;
+ }
+ priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
+
+ ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
+ if (ret) {
+ PMD_DRV_LOG(ERR, PMD,
+ "dpci setup failed with err code: %d", ret);
+ return ret;
+ }
+ priv->max_event_queues++;
+ } while (dpcon_dev && dpci_dev);
return 0;
+fail:
+ return -EFAULT;
}
static int
@@ -61,9 +208,7 @@
name = rte_vdev_device_name(vdev);
PMD_DRV_LOG(INFO, "Closing %s", name);
- RTE_SET_USED(name);
-
- return 0;
+ return rte_event_pmd_vdev_uninit(name);
}
static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h
index b151502..01de73c 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.h
+++ b/drivers/event/dpaa2/dpaa2_eventdev.h
@@ -52,6 +52,16 @@
#define PMD_DRV_ERR(fmt, args...) \
RTE_LOG(ERR, PMD, "%s(): " fmt "\n", __func__, ## args)
+#define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0
+
+#define DPAA2_EVENT_MAX_QUEUES 16
+
+enum {
+ DPAA2_EVENT_DPCI_PARALLEL_QUEUE,
+ DPAA2_EVENT_DPCI_ATOMIC_QUEUE,
+ DPAA2_EVENT_DPCI_MAX_QUEUES
+};
+
struct dpaa2_dpcon_dev {
TAILQ_ENTRY(dpaa2_dpcon_dev) next;
struct fsl_mc_io dpcon;
@@ -63,6 +73,18 @@ struct dpaa2_dpcon_dev {
uint8_t channel_index;
};
+struct evq_info_t {
+ /* DPcon device */
+ struct dpaa2_dpcon_dev *dpcon;
+ /* Attached DPCI device */
+ struct dpaa2_dpci_dev *dpci;
+};
+
+struct dpaa2_eventdev {
+ struct evq_info_t evq_info[DPAA2_EVENT_MAX_QUEUES];
+ uint8_t max_event_queues;
+};
+
struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device
2017-05-25 18:07 ` [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device Nipun Gupta
@ 2017-05-31 15:10 ` Jerin Jacob
2017-06-01 10:25 ` Nipun Gupta
0 siblings, 1 reply; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 15:10 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:41 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 10/20] event/dpaa2: add initialization of event device
> X-Mailer: git-send-email 1.9.1
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> ---
> drivers/event/dpaa2/dpaa2_eventdev.c | 153 ++++++++++++++++++++++++++++++++++-
> drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++++
> 2 files changed, 171 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
> index 191901e..7fa17f2 100644
> --- a/drivers/event/dpaa2/dpaa2_eventdev.c
> +++ b/drivers/event/dpaa2/dpaa2_eventdev.c
> @@ -30,17 +30,164 @@
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> +#include <assert.h>
> +#include <stdio.h>
> +#include <stdbool.h>
> +#include <errno.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdint.h>
> +#include <sys/epoll.h>
> +
> +#include <rte_byteorder.h>
> +#include <rte_common.h>
> +#include <rte_debug.h>
> +#include <rte_dev.h>
> #include <rte_eal.h>
> +#include <rte_log.h>
> +#include <rte_memory.h>
> +#include <rte_memzone.h>
> +#include <rte_malloc.h>
> +#include <rte_pci.h>
> +#include <rte_lcore.h>
> #include <rte_vdev.h>
> +#include <rte_fslmc.h>
> +#include <rte_atomic.h>
Maintain alphabetical order in header inclusion.
>
> +#include <fslmc_vfio.h>
> +#include <dpaa2_hw_pvt.h>
> +#include <dpaa2_hw_mempool.h>
> +#include <dpaa2_hw_dpio.h>
> #include "dpaa2_eventdev.h"
> +#include <portal/dpaa2_hw_pvt.h>
> +#include <mc/fsl_dpci.h>
> +
> +/* Clarifications
> + * Evendev = SoC Instance
> + * Eventport = DPIO Instance
> + * Eventqueue = DPCON Instance
> + * 1 Eventdev can have N Eventqueue
> + * Soft Event Flow is DPCI Instance
> + */
> +
> +static uint16_t
> +dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
> + uint16_t nb_events)
> +{
> + RTE_SET_USED(port);
> + RTE_SET_USED(ev);
> + RTE_SET_USED(nb_events);
> +
> + return 0;
> +}
> +
> +static uint16_t
> +dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
> +{
> + return dpaa2_eventdev_enqueue_burst(port, ev, 1);
> +}
> +
> +static uint16_t
> +dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
> + uint16_t nb_events, uint64_t timeout_ticks)
> +{
> + RTE_SET_USED(port);
> + RTE_SET_USED(ev);
> + RTE_SET_USED(nb_events);
> + RTE_SET_USED(timeout_ticks);
> +
> + return 0;
> +}
> +
> +static uint16_t
> +dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
> + uint64_t timeout_ticks)
> +{
> + return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
> +}
> +
> +static const struct rte_eventdev_ops dpaa2_eventdev_ops;
> +
> +static int
> +dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
> + struct dpaa2_dpcon_dev *dpcon_dev)
> +{
> + struct dpci_rx_queue_cfg rx_queue_cfg;
> + int ret, i;
> +
> + /*Do settings to get the frame on a DPCON object*/
> + rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST;
> + rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
> + rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
> + rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
> +
> + for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
> + rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
> + ret = dpci_set_rx_queue(&dpci_dev->dpci,
> + CMD_PRI_LOW,
> + dpci_dev->token, i,
> + &rx_queue_cfg);
> + if (ret) {
> + PMD_DRV_LOG(ERR, PMD,
> + "set_rx_q failed with err code: %d", ret);
> + return ret;
> + }
> + }
> + return 0;
> +}
>
> static int
> dpaa2_eventdev_create(const char *name)
> {
> - RTE_SET_USED(name);
> + struct rte_eventdev *eventdev;
> + struct dpaa2_eventdev *priv;
> + struct dpaa2_dpcon_dev *dpcon_dev = NULL;
> + struct dpaa2_dpci_dev *dpci_dev = NULL;
> + int ret;
> +
> + eventdev = rte_event_pmd_vdev_init(name,
> + sizeof(struct dpaa2_eventdev),
> + rte_socket_id());
> + if (eventdev == NULL) {
> + PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
> + goto fail;
> + }
> +
> + eventdev->dev_ops = &dpaa2_eventdev_ops;
> + eventdev->schedule = NULL;
> + eventdev->enqueue = dpaa2_eventdev_enqueue;
> + eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
> + eventdev->dequeue = dpaa2_eventdev_dequeue;
> + eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
If it makes senses, you can return from here if its in multi process mode.
> +
> + priv = eventdev->data->dev_private;
> + priv->max_event_queues = 0;
> +
> + do {
> + dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
> + if (!dpcon_dev)
> + break;
> + priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
> +
> + dpci_dev = rte_dpaa2_alloc_dpci_dev();
> + if (!dpci_dev) {
> + rte_dpaa2_free_dpcon_dev(dpcon_dev);
> + break;
> + }
> + priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
> +
> + ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
> + if (ret) {
> + PMD_DRV_LOG(ERR, PMD,
> + "dpci setup failed with err code: %d", ret);
> + return ret;
> + }
> + priv->max_event_queues++;
> + } while (dpcon_dev && dpci_dev);
>
> return 0;
> +fail:
> + return -EFAULT;
> }
>
> static int
> @@ -61,9 +208,7 @@
> name = rte_vdev_device_name(vdev);
> PMD_DRV_LOG(INFO, "Closing %s", name);
>
> - RTE_SET_USED(name);
> -
> - return 0;
> + return rte_event_pmd_vdev_uninit(name);
> }
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device
2017-05-31 15:10 ` Jerin Jacob
@ 2017-06-01 10:25 ` Nipun Gupta
2017-06-01 10:39 ` Jerin Jacob
0 siblings, 1 reply; 34+ messages in thread
From: Nipun Gupta @ 2017-06-01 10:25 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, Hemant Agrawal, harry.van.haaren, bruce.richardson,
gage.eads, Shreyansh Jain
> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Wednesday, May 31, 2017 20:40
> To: Nipun Gupta <nipun.gupta@nxp.com>
> Cc: dev@dpdk.org; Hemant Agrawal <hemant.agrawal@nxp.com>;
> harry.van.haaren@intel.com; bruce.richardson@intel.com;
> gage.eads@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>
> Subject: Re: [PATCH 10/20] event/dpaa2: add initialization of event device
>
> -----Original Message-----
> > Date: Thu, 25 May 2017 23:37:41 +0530
> > From: Nipun Gupta <nipun.gupta@nxp.com>
> > To: dev@dpdk.org
> > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > <nipun.gupta@nxp.com>
> > Subject: [PATCH 10/20] event/dpaa2: add initialization of event device
> > X-Mailer: git-send-email 1.9.1
> >
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > ---
> > drivers/event/dpaa2/dpaa2_eventdev.c | 153
> ++++++++++++++++++++++++++++++++++-
> > drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++++
> > 2 files changed, 171 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c
> b/drivers/event/dpaa2/dpaa2_eventdev.c
> > index 191901e..7fa17f2 100644
> > --- a/drivers/event/dpaa2/dpaa2_eventdev.c
> > +++ b/drivers/event/dpaa2/dpaa2_eventdev.c
> > @@ -30,17 +30,164 @@
> > * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> > */
> >
> > +#include <assert.h>
> > +#include <stdio.h>
> > +#include <stdbool.h>
> > +#include <errno.h>
> > +#include <stdint.h>
> > +#include <string.h>
> > +#include <stdint.h>
> > +#include <sys/epoll.h>
> > +
> > +#include <rte_byteorder.h>
> > +#include <rte_common.h>
> > +#include <rte_debug.h>
> > +#include <rte_dev.h>
> > #include <rte_eal.h>
> > +#include <rte_log.h>
> > +#include <rte_memory.h>
> > +#include <rte_memzone.h>
> > +#include <rte_malloc.h>
> > +#include <rte_pci.h>
> > +#include <rte_lcore.h>
> > #include <rte_vdev.h>
> > +#include <rte_fslmc.h>
> > +#include <rte_atomic.h>
>
> Maintain alphabetical order in header inclusion.
Thank you for the review.
Regarding this I check most of the c files in DPDK and do not see that alphabetical
being maintained in the header file inclusions. Are you suggesting to have an alphabetical
order here across all inclusions of rte* as well as gcc standard header files (combined) or
to have them ordered separately?
>
> >
> > +#include <fslmc_vfio.h>
> > +#include <dpaa2_hw_pvt.h>
> > +#include <dpaa2_hw_mempool.h>
> > +#include <dpaa2_hw_dpio.h>
> > #include "dpaa2_eventdev.h"
> > +#include <portal/dpaa2_hw_pvt.h>
> > +#include <mc/fsl_dpci.h>
> > +
> > +/* Clarifications
> > + * Evendev = SoC Instance
> > + * Eventport = DPIO Instance
> > + * Eventqueue = DPCON Instance
> > + * 1 Eventdev can have N Eventqueue
> > + * Soft Event Flow is DPCI Instance
> > + */
> > +
> > +static uint16_t
> > +dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
> > + uint16_t nb_events)
> > +{
> > + RTE_SET_USED(port);
> > + RTE_SET_USED(ev);
> > + RTE_SET_USED(nb_events);
> > +
> > + return 0;
> > +}
> > +
> > +static uint16_t
> > +dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
> > +{
> > + return dpaa2_eventdev_enqueue_burst(port, ev, 1);
> > +}
> > +
> > +static uint16_t
> > +dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
> > + uint16_t nb_events, uint64_t timeout_ticks)
> > +{
> > + RTE_SET_USED(port);
> > + RTE_SET_USED(ev);
> > + RTE_SET_USED(nb_events);
> > + RTE_SET_USED(timeout_ticks);
> > +
> > + return 0;
> > +}
> > +
> > +static uint16_t
> > +dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
> > + uint64_t timeout_ticks)
> > +{
> > + return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
> > +}
> > +
> > +static const struct rte_eventdev_ops dpaa2_eventdev_ops;
> > +
> > +static int
> > +dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
> > + struct dpaa2_dpcon_dev *dpcon_dev)
> > +{
> > + struct dpci_rx_queue_cfg rx_queue_cfg;
> > + int ret, i;
> > +
> > + /*Do settings to get the frame on a DPCON object*/
> > + rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST;
> > + rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
> > + rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
> > + rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
> > +
> > + for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
> > + rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
> > + ret = dpci_set_rx_queue(&dpci_dev->dpci,
> > + CMD_PRI_LOW,
> > + dpci_dev->token, i,
> > + &rx_queue_cfg);
> > + if (ret) {
> > + PMD_DRV_LOG(ERR, PMD,
> > + "set_rx_q failed with err code: %d", ret);
> > + return ret;
> > + }
> > + }
> > + return 0;
> > +}
> >
> > static int
> > dpaa2_eventdev_create(const char *name)
> > {
> > - RTE_SET_USED(name);
> > + struct rte_eventdev *eventdev;
> > + struct dpaa2_eventdev *priv;
> > + struct dpaa2_dpcon_dev *dpcon_dev = NULL;
> > + struct dpaa2_dpci_dev *dpci_dev = NULL;
> > + int ret;
> > +
> > + eventdev = rte_event_pmd_vdev_init(name,
> > + sizeof(struct dpaa2_eventdev),
> > + rte_socket_id());
> > + if (eventdev == NULL) {
> > + PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
> > + goto fail;
> > + }
> > +
> > + eventdev->dev_ops = &dpaa2_eventdev_ops;
> > + eventdev->schedule = NULL;
> > + eventdev->enqueue = dpaa2_eventdev_enqueue;
> > + eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
> > + eventdev->dequeue = dpaa2_eventdev_dequeue;
> > + eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
>
> If it makes senses, you can return from here if its in multi process mode.
Makes sense. Ill update this in next version.
>
> > +
> > + priv = eventdev->data->dev_private;
> > + priv->max_event_queues = 0;
> > +
> > + do {
> > + dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
> > + if (!dpcon_dev)
> > + break;
> > + priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
> > +
> > + dpci_dev = rte_dpaa2_alloc_dpci_dev();
> > + if (!dpci_dev) {
> > + rte_dpaa2_free_dpcon_dev(dpcon_dev);
> > + break;
> > + }
> > + priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
> > +
> > + ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
> > + if (ret) {
> > + PMD_DRV_LOG(ERR, PMD,
> > + "dpci setup failed with err code: %d", ret);
> > + return ret;
> > + }
> > + priv->max_event_queues++;
> > + } while (dpcon_dev && dpci_dev);
> >
> > return 0;
> > +fail:
> > + return -EFAULT;
> > }
> >
> > static int
> > @@ -61,9 +208,7 @@
> > name = rte_vdev_device_name(vdev);
> > PMD_DRV_LOG(INFO, "Closing %s", name);
> >
> > - RTE_SET_USED(name);
> > -
> > - return 0;
> > + return rte_event_pmd_vdev_uninit(name);
> > }
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device
2017-06-01 10:25 ` Nipun Gupta
@ 2017-06-01 10:39 ` Jerin Jacob
0 siblings, 0 replies; 34+ messages in thread
From: Jerin Jacob @ 2017-06-01 10:39 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, Hemant Agrawal, harry.van.haaren, bruce.richardson,
gage.eads, Shreyansh Jain
-----Original Message-----
> Date: Thu, 1 Jun 2017 10:25:02 +0000
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> CC: "dev@dpdk.org" <dev@dpdk.org>, Hemant Agrawal <hemant.agrawal@nxp.com>,
> "harry.van.haaren@intel.com" <harry.van.haaren@intel.com>,
> "bruce.richardson@intel.com" <bruce.richardson@intel.com>,
> "gage.eads@intel.com" <gage.eads@intel.com>, Shreyansh Jain
> <shreyansh.jain@nxp.com>
> Subject: RE: [PATCH 10/20] event/dpaa2: add initialization of event device
>
>
>
> > -----Original Message-----
> > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> > Sent: Wednesday, May 31, 2017 20:40
> > To: Nipun Gupta <nipun.gupta@nxp.com>
> > Cc: dev@dpdk.org; Hemant Agrawal <hemant.agrawal@nxp.com>;
> > harry.van.haaren@intel.com; bruce.richardson@intel.com;
> > gage.eads@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>
> > Subject: Re: [PATCH 10/20] event/dpaa2: add initialization of event device
> >
> > -----Original Message-----
> > > Date: Thu, 25 May 2017 23:37:41 +0530
> > > From: Nipun Gupta <nipun.gupta@nxp.com>
> > > To: dev@dpdk.org
> > > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > > <nipun.gupta@nxp.com>
> > > Subject: [PATCH 10/20] event/dpaa2: add initialization of event device
> > > X-Mailer: git-send-email 1.9.1
> > >
> > > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > > ---
> > > drivers/event/dpaa2/dpaa2_eventdev.c | 153
> > ++++++++++++++++++++++++++++++++++-
> > > drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++++
> > > 2 files changed, 171 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c
> > b/drivers/event/dpaa2/dpaa2_eventdev.c
> > > index 191901e..7fa17f2 100644
> > > --- a/drivers/event/dpaa2/dpaa2_eventdev.c
> > > +++ b/drivers/event/dpaa2/dpaa2_eventdev.c
> > > @@ -30,17 +30,164 @@
> > > * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> > DAMAGE.
> > > */
> > >
> > > +#include <assert.h>
> > > +#include <stdio.h>
> > > +#include <stdbool.h>
> > > +#include <errno.h>
> > > +#include <stdint.h>
> > > +#include <string.h>
> > > +#include <stdint.h>
> > > +#include <sys/epoll.h>
> > > +
> > > +#include <rte_byteorder.h>
> > > +#include <rte_common.h>
> > > +#include <rte_debug.h>
> > > +#include <rte_dev.h>
> > > #include <rte_eal.h>
> > > +#include <rte_log.h>
> > > +#include <rte_memory.h>
> > > +#include <rte_memzone.h>
> > > +#include <rte_malloc.h>
> > > +#include <rte_pci.h>
> > > +#include <rte_lcore.h>
> > > #include <rte_vdev.h>
> > > +#include <rte_fslmc.h>
> > > +#include <rte_atomic.h>
> >
> > Maintain alphabetical order in header inclusion.
>
> Thank you for the review.
>
> Regarding this I check most of the c files in DPDK and do not see that alphabetical
> being maintained in the header file inclusions. Are you suggesting to have an alphabetical
> order here across all inclusions of rte* as well as gcc standard header files (combined) or
> to have them ordered separately?
Just the rte_*.h header files in the new files.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [dpdk-dev] [PATCH 11/20] bus/fslmc: add support for static dequeue from portal
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (9 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 10/20] event/dpaa2: add initialization of event device Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions Nipun Gupta
` (9 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/mc/dpio.c | 44 +++++++++++++++++++++++++++++
drivers/bus/fslmc/mc/fsl_dpio.h | 30 ++++++++++++++++++++
drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 1 +
drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 ++
4 files changed, 77 insertions(+)
diff --git a/drivers/bus/fslmc/mc/dpio.c b/drivers/bus/fslmc/mc/dpio.c
index d84232a..3553952 100644
--- a/drivers/bus/fslmc/mc/dpio.c
+++ b/drivers/bus/fslmc/mc/dpio.c
@@ -257,6 +257,50 @@ int dpio_get_stashing_destination(struct fsl_mc_io *mc_io,
return 0;
}
+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int dpcon_id,
+ uint8_t *channel_index)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ADD_STATIC_DEQUEUE_CHANNEL,
+ cmd_flags,
+ token);
+ DPIO_CMD_ADD_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPIO_RSP_ADD_STATIC_DEQUEUE_CHANNEL(cmd, *channel_index);
+
+ return 0;
+}
+
+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int dpcon_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(
+ DPIO_CMDID_REMOVE_STATIC_DEQUEUE_CHANNEL,
+ cmd_flags,
+ token);
+ DPIO_CMD_REMOVE_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpio_get_api_version(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t *major_ver,
diff --git a/drivers/bus/fslmc/mc/fsl_dpio.h b/drivers/bus/fslmc/mc/fsl_dpio.h
index 6d86f07..39b572d 100644
--- a/drivers/bus/fslmc/mc/fsl_dpio.h
+++ b/drivers/bus/fslmc/mc/fsl_dpio.h
@@ -230,6 +230,36 @@ int dpio_get_stashing_destination(struct fsl_mc_io *mc_io,
uint8_t *sdest);
/**
+ * dpio_add_static_dequeue_channel() - Add a static dequeue channel.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPIO object
+ * @dpcon_id: DPCON object ID
+ * @channel_index: Returned channel index to be used in qbman API
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int dpcon_id,
+ uint8_t *channel_index);
+
+/**
+ * dpio_remove_static_dequeue_channel() - Remove a static dequeue channel.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPIO object
+ * @dpcon_id: DPCON object ID
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int dpcon_id);
+
+/**
* struct dpio_attr - Structure representing DPIO attributes
* @id: DPIO object ID
* @qbman_portal_ce_offset: offset of the software portal cache-enabled area
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
index 4269800..77efe37 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
@@ -42,6 +42,7 @@ struct dpaa2_io_portal_t {
struct dpaa2_dpio_dev *sec_dpio_dev;
uint64_t net_tid;
uint64_t sec_tid;
+ void *eventdev;
};
/*! Global per thread DPIO portal */
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index fdc6e21..79cb648 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -58,6 +58,8 @@ DPDK_17.08 {
dpci_set_rx_queue;
dpcon_open;
dpcon_get_attributes;
+ dpio_add_static_dequeue_channel;
+ dpio_remove_static_dequeue_channel;
qbman_eq_desc_set_dca;
qbman_get_dqrr_from_idx;
qbman_get_dqrr_idx;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (10 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 11/20] bus/fslmc: add support for static dequeue from portal Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-31 15:20 ` Jerin Jacob
2017-05-31 15:29 ` Jerin Jacob
2017-05-25 18:07 ` [dpdk-dev] [PATCH 13/20] bus/fslmc: support enqueue with multiple enqueue descriptors Nipun Gupta
` (8 subsequent siblings)
20 siblings, 2 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
This patch adds all the configuration API's for DPAA2 eventdev
including device config, start, stop & port and queue
related API's
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/event/dpaa2/dpaa2_eventdev.c | 283 ++++++++++++++++++++++++++++++++++-
drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++
2 files changed, 304 insertions(+), 1 deletion(-)
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index 7fa17f2..cfb52bb 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -106,7 +106,288 @@
return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
}
-static const struct rte_eventdev_ops dpaa2_eventdev_ops;
+static void
+dpaa2_eventdev_info_get(struct rte_eventdev *dev,
+ struct rte_event_dev_info *dev_info)
+{
+ struct dpaa2_eventdev *priv = dev->data->dev_private;
+
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+
+ memset(dev_info, 0, sizeof(struct rte_event_dev_info));
+ dev_info->min_dequeue_timeout_ns =
+ DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
+ dev_info->max_dequeue_timeout_ns =
+ DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
+ dev_info->dequeue_timeout_ns =
+ DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
+ dev_info->max_event_queues = priv->max_event_queues;
+ dev_info->max_event_queue_flows =
+ DPAA2_EVENT_MAX_QUEUE_FLOWS;
+ dev_info->max_event_queue_priority_levels =
+ DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
+ dev_info->max_event_priority_levels =
+ DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
+ dev_info->max_event_ports = RTE_MAX_LCORE;
+ dev_info->max_event_port_dequeue_depth =
+ DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
+ dev_info->max_event_port_enqueue_depth =
+ DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
+ dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
+ dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED;
+}
+
+static int
+dpaa2_eventdev_configure(const struct rte_eventdev *dev)
+{
+ struct dpaa2_eventdev *priv = dev->data->dev_private;
+ struct rte_event_dev_config *conf = &dev->data->dev_conf;
+
+ PMD_DRV_FUNC_TRACE();
+
+ priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
+ priv->nb_event_queues = conf->nb_event_queues;
+ priv->nb_event_ports = conf->nb_event_ports;
+ priv->nb_event_queue_flows = conf->nb_event_queue_flows;
+ priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
+ priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
+ priv->event_dev_cfg = conf->event_dev_cfg;
+
+ PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
+ return 0;
+}
+
+static int
+dpaa2_eventdev_start(struct rte_eventdev *dev)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+
+ return 0;
+}
+
+static void
+dpaa2_eventdev_stop(struct rte_eventdev *dev)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+}
+
+static int
+dpaa2_eventdev_close(struct rte_eventdev *dev)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+
+ return 0;
+}
+
+static void
+dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
+ struct rte_event_queue_conf *queue_conf)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(queue_id);
+ RTE_SET_USED(queue_conf);
+
+ queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
+ queue_conf->nb_atomic_order_sequences = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
+ queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
+ queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
+}
+
+static void
+dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(queue_id);
+}
+
+static int
+dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
+ const struct rte_event_queue_conf *queue_conf)
+{
+ struct dpaa2_eventdev *priv = dev->data->dev_private;
+ struct evq_info_t *evq_info =
+ &priv->evq_info[queue_id];
+
+ PMD_DRV_FUNC_TRACE();
+
+ evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
+
+ return 0;
+}
+
+static void
+dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
+ struct rte_event_port_conf *port_conf)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(port_id);
+ RTE_SET_USED(port_conf);
+
+ port_conf->new_event_threshold =
+ DPAA2_EVENT_MAX_NUM_EVENTS;
+ port_conf->dequeue_depth =
+ DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
+ port_conf->enqueue_depth =
+ DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
+}
+
+static void
+dpaa2_eventdev_port_release(void *port)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(port);
+}
+
+static int
+dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
+ const struct rte_event_port_conf *port_conf)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(port_conf);
+
+ if (!dpaa2_io_portal[port_id].dpio_dev) {
+ dpaa2_io_portal[port_id].dpio_dev =
+ dpaa2_get_qbman_swp(port_id);
+ rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
+ if (!dpaa2_io_portal[port_id].dpio_dev)
+ return -1;
+ }
+
+ dpaa2_io_portal[port_id].eventdev = dev;
+ dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
+ return 0;
+}
+
+static int
+dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
+ uint8_t queues[], uint16_t nb_unlinks)
+{
+ struct dpaa2_eventdev *priv = dev->data->dev_private;
+ struct dpaa2_io_portal_t *dpaa2_portal = port;
+ struct evq_info_t *evq_info;
+ int i;
+
+ PMD_DRV_FUNC_TRACE();
+
+ for (i = 0; i < nb_unlinks; i++) {
+ evq_info = &priv->evq_info[queues[i]];
+ qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
+ evq_info->dpcon->channel_index, 0);
+ dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
+ 0, dpaa2_portal->dpio_dev->token,
+ evq_info->dpcon->dpcon_id);
+ evq_info->link = 0;
+ }
+
+ return (int)nb_unlinks;
+}
+
+static int
+dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
+ const uint8_t queues[], const uint8_t priorities[],
+ uint16_t nb_links)
+{
+ struct dpaa2_eventdev *priv = dev->data->dev_private;
+ struct dpaa2_io_portal_t *dpaa2_portal = port;
+ struct evq_info_t *evq_info;
+ uint8_t channel_index;
+ int ret, i, n;
+
+ PMD_DRV_FUNC_TRACE();
+
+ for (i = 0; i < nb_links; i++) {
+ evq_info = &priv->evq_info[queues[i]];
+ if (evq_info->link)
+ continue;
+
+ ret = dpio_add_static_dequeue_channel(
+ dpaa2_portal->dpio_dev->dpio,
+ CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
+ evq_info->dpcon->dpcon_id, &channel_index);
+ if (ret < 0) {
+ PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
+ ret);
+ goto err;
+ }
+
+ qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
+ channel_index, 1);
+ evq_info->dpcon->channel_index = channel_index;
+ evq_info->link = 1;
+ }
+
+ RTE_SET_USED(priorities);
+
+ return (int)nb_links;
+err:
+ for (n = 0; n < i; n++) {
+ evq_info = &priv->evq_info[queues[n]];
+ qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
+ evq_info->dpcon->channel_index, 0);
+ dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
+ 0, dpaa2_portal->dpio_dev->token,
+ evq_info->dpcon->dpcon_id);
+ evq_info->link = 0;
+ }
+ return ret;
+}
+
+static int
+dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
+ uint64_t *timeout_ticks)
+{
+ uint32_t scale = 1;
+
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+ *timeout_ticks = ns * scale;
+
+ return 0;
+}
+
+static void
+dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
+{
+ PMD_DRV_FUNC_TRACE();
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(f);
+}
+
+static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
+ .dev_infos_get = dpaa2_eventdev_info_get,
+ .dev_configure = dpaa2_eventdev_configure,
+ .dev_start = dpaa2_eventdev_start,
+ .dev_stop = dpaa2_eventdev_stop,
+ .dev_close = dpaa2_eventdev_close,
+ .queue_def_conf = dpaa2_eventdev_queue_def_conf,
+ .queue_setup = dpaa2_eventdev_queue_setup,
+ .queue_release = dpaa2_eventdev_queue_release,
+ .port_def_conf = dpaa2_eventdev_port_def_conf,
+ .port_setup = dpaa2_eventdev_port_setup,
+ .port_release = dpaa2_eventdev_port_release,
+ .port_link = dpaa2_eventdev_port_link,
+ .port_unlink = dpaa2_eventdev_port_unlink,
+ .timeout_ticks = dpaa2_eventdev_timeout_ticks,
+ .dump = dpaa2_eventdev_dump
+};
static int
dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h
index 01de73c..4027852 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.h
+++ b/drivers/event/dpaa2/dpaa2_eventdev.h
@@ -55,6 +55,17 @@
#define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0
#define DPAA2_EVENT_MAX_QUEUES 16
+#define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT 1
+#define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1)
+#define DPAA2_EVENT_MAX_QUEUE_FLOWS 2048
+#define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8
+#define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS 0
+#define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH 8
+#define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH 8
+#define DPAA2_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1)
+
+#define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS 2048
+#define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES 2048
enum {
DPAA2_EVENT_DPCI_PARALLEL_QUEUE,
@@ -78,11 +89,22 @@ struct evq_info_t {
struct dpaa2_dpcon_dev *dpcon;
/* Attached DPCI device */
struct dpaa2_dpci_dev *dpci;
+ /* Configuration provided by the user */
+ uint32_t event_queue_cfg;
+ uint8_t link;
};
struct dpaa2_eventdev {
struct evq_info_t evq_info[DPAA2_EVENT_MAX_QUEUES];
+ uint32_t dequeue_timeout_ns;
uint8_t max_event_queues;
+ uint8_t nb_event_queues;
+ uint8_t nb_event_ports;
+ uint8_t resvd_1;
+ uint32_t nb_event_queue_flows;
+ uint32_t nb_event_port_dequeue_depth;
+ uint32_t nb_event_port_enqueue_depth;
+ uint32_t event_dev_cfg;
};
struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions
2017-05-25 18:07 ` [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions Nipun Gupta
@ 2017-05-31 15:20 ` Jerin Jacob
2017-05-31 15:29 ` Jerin Jacob
1 sibling, 0 replies; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 15:20 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:43 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 12/20] event/dpaa2: add configuration functions
> X-Mailer: git-send-email 1.9.1
>
> This patch adds all the configuration API's for DPAA2 eventdev
> including device config, start, stop & port and queue
> related API's
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> ---
> +static void
> +dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
> + struct rte_event_queue_conf *queue_conf)
> +{
> + PMD_DRV_FUNC_TRACE();
> +
> + RTE_SET_USED(dev);
> + RTE_SET_USED(queue_id);
> + RTE_SET_USED(queue_conf);
> +
> + queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
> + queue_conf->nb_atomic_order_sequences = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
> + queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
If RTE_EVENT_QUEUE_CFG_ALL_TYPES is supported then add
RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES in rte_event_dev_info.event_dev_cap
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions
2017-05-25 18:07 ` [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions Nipun Gupta
2017-05-31 15:20 ` Jerin Jacob
@ 2017-05-31 15:29 ` Jerin Jacob
2017-06-01 11:39 ` Nipun Gupta
1 sibling, 1 reply; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 15:29 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:43 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 12/20] event/dpaa2: add configuration functions
> X-Mailer: git-send-email 1.9.1
>
> This patch adds all the configuration API's for DPAA2 eventdev
> including device config, start, stop & port and queue
> related API's
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> ---
> drivers/event/dpaa2/dpaa2_eventdev.c | 283 ++++++++++++++++++++++++++++++++++-
> drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++
> 2 files changed, 304 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
> index 7fa17f2..cfb52bb 100644
> --- a/drivers/event/dpaa2/dpaa2_eventdev.c
> +++ b/drivers/event/dpaa2/dpaa2_eventdev.c
> @@ -106,7 +106,288 @@
> return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
> }
>
> +static int
> +dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
> + const struct rte_event_queue_conf *queue_conf)
> +{
> + struct dpaa2_eventdev *priv = dev->data->dev_private;
> + struct evq_info_t *evq_info =
> + &priv->evq_info[queue_id];
> +
> + PMD_DRV_FUNC_TRACE();
> +
> + evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
Based on the documentation, it looks like ORDERED sched type is not
supported. If so, return an error when queue config request is
RTE_EVENT_QUEUE_CFG_ORDERED_ONLY.
On the same lines, default_queue_setup() returns
RTE_EVENT_QUEUE_CFG_ALL_TYPES as default value. If ORDERED sched type
is not supported then I think, RTE_EVENT_QUEUE_CFG_ALL_TYPES
can not be used as default or configured.
> +
> + return 0;
> +}
> +
> +static void
> +dpaa2_eventdev_port_release(void *port)
> +{
> + PMD_DRV_FUNC_TRACE();
> +
> + RTE_SET_USED(port);
> +}
> +
> +static int
> +dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
> + const struct rte_event_port_conf *port_conf)
> +{
> + PMD_DRV_FUNC_TRACE();
> +
> + RTE_SET_USED(port_conf);
> +
> + if (!dpaa2_io_portal[port_id].dpio_dev) {
> + dpaa2_io_portal[port_id].dpio_dev =
> + dpaa2_get_qbman_swp(port_id);
> + rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
> + if (!dpaa2_io_portal[port_id].dpio_dev)
> + return -1;
> + }
> +
> + dpaa2_io_portal[port_id].eventdev = dev;
> + dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions
2017-05-31 15:29 ` Jerin Jacob
@ 2017-06-01 11:39 ` Nipun Gupta
0 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-06-01 11:39 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, Hemant Agrawal, harry.van.haaren, bruce.richardson,
gage.eads, Shreyansh Jain
> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Wednesday, May 31, 2017 20:59
> To: Nipun Gupta <nipun.gupta@nxp.com>
> Cc: dev@dpdk.org; Hemant Agrawal <hemant.agrawal@nxp.com>;
> harry.van.haaren@intel.com; bruce.richardson@intel.com;
> gage.eads@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>
> Subject: Re: [PATCH 12/20] event/dpaa2: add configuration functions
>
> -----Original Message-----
> > Date: Thu, 25 May 2017 23:37:43 +0530
> > From: Nipun Gupta <nipun.gupta@nxp.com>
> > To: dev@dpdk.org
> > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > <nipun.gupta@nxp.com>
> > Subject: [PATCH 12/20] event/dpaa2: add configuration functions
> > X-Mailer: git-send-email 1.9.1
> >
> > This patch adds all the configuration API's for DPAA2 eventdev
> > including device config, start, stop & port and queue
> > related API's
> >
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > ---
> > drivers/event/dpaa2/dpaa2_eventdev.c | 283
> ++++++++++++++++++++++++++++++++++-
> > drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++
> > 2 files changed, 304 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c
> b/drivers/event/dpaa2/dpaa2_eventdev.c
> > index 7fa17f2..cfb52bb 100644
> > --- a/drivers/event/dpaa2/dpaa2_eventdev.c
> > +++ b/drivers/event/dpaa2/dpaa2_eventdev.c
> > @@ -106,7 +106,288 @@
> > return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
> > }
> >
> > +static int
> > +dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
> > + const struct rte_event_queue_conf *queue_conf)
> > +{
> > + struct dpaa2_eventdev *priv = dev->data->dev_private;
> > + struct evq_info_t *evq_info =
> > + &priv->evq_info[queue_id];
> > +
> > + PMD_DRV_FUNC_TRACE();
> > +
> > + evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
>
> Based on the documentation, it looks like ORDERED sched type is not
> supported. If so, return an error when queue config request is
> RTE_EVENT_QUEUE_CFG_ORDERED_ONLY.
>
> On the same lines, default_queue_setup() returns
> RTE_EVENT_QUEUE_CFG_ALL_TYPES as default value. If ORDERED sched type
> is not supported then I think, RTE_EVENT_QUEUE_CFG_ALL_TYPES
> can not be used as default or configured.
Yes, Right now we are supporting only parallel and atomic queues and waiting
for our MC firmware to have support for ordered queues in case of enqueue
from software. I need to update my code with this. Ill update this in v2.
Thanks
>
> > +
> > + return 0;
> > +}
> > +
> > +static void
> > +dpaa2_eventdev_port_release(void *port)
> > +{
> > + PMD_DRV_FUNC_TRACE();
> > +
> > + RTE_SET_USED(port);
> > +}
> > +
> > +static int
> > +dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
> > + const struct rte_event_port_conf *port_conf)
> > +{
> > + PMD_DRV_FUNC_TRACE();
> > +
> > + RTE_SET_USED(port_conf);
> > +
> > + if (!dpaa2_io_portal[port_id].dpio_dev) {
> > + dpaa2_io_portal[port_id].dpio_dev =
> > + dpaa2_get_qbman_swp(port_id);
> > + rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev-
> >ref_count);
> > + if (!dpaa2_io_portal[port_id].dpio_dev)
> > + return -1;
> > + }
> > +
> > + dpaa2_io_portal[port_id].eventdev = dev;
> > + dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
> > + return 0;
> > +}
> > +
^ permalink raw reply [flat|nested] 34+ messages in thread
* [dpdk-dev] [PATCH 13/20] bus/fslmc: support enqueue with multiple enqueue descriptors
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (11 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 14/20] bus/fslmc: add callback per queue to enable Nipun Gupta
` (7 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
This patch adds the QBMAN API which support multiple enqueue
descriptors.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 14 +++++
drivers/bus/fslmc/qbman/qbman_portal.c | 70 ++++++++++++++++++++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 1 +
3 files changed, 85 insertions(+)
diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
index 7731772..39407c8 100644
--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
@@ -883,6 +883,20 @@ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
*/
int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
const struct qbman_fd *fd);
+/**
+ * qbman_swp_enqueue_multiple_eqdesc() - Enqueue multiple frames with separte
+ * enqueue descriptors.
+ * @s: the software portal used for enqueue.
+ * @d: the enqueue descriptors
+ * @fd: the frame descriptor to be enqueued.
+ * @num_frames: the number of the frames to be enqueued.
+ *
+ * Return the number of enqueued frames, -EBUSY if the EQCR is not ready.
+ */
+int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,
+ const struct qbman_eq_desc *d,
+ const struct qbman_fd *fd,
+ int num_frames);
/* TODO:
* qbman_swp_enqueue_thresh() - Set threshold for EQRI interrupt.
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index 5d407cc..3f1b31d 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -574,6 +574,76 @@ int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
return qbman_swp_enqueue_ring_mode(s, d, fd);
}
+int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,
+ const struct qbman_eq_desc *d,
+ const struct qbman_fd *fd,
+ int num_frames)
+{
+ uint32_t *p;
+ const uint32_t *cl = qb_cl(d);
+ uint32_t eqcr_ci, eqcr_pi;
+ uint8_t diff;
+ int i, num_enqueued = 0;
+ uint64_t addr_cena;
+
+ if (!s->eqcr.available) {
+ eqcr_ci = s->eqcr.ci;
+ s->eqcr.ci = qbman_cena_read_reg(&s->sys,
+ QBMAN_CENA_SWP_EQCR_CI) & 0xF;
+ diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
+ eqcr_ci, s->eqcr.ci);
+ s->eqcr.available += diff;
+ if (!diff)
+ return 0;
+ }
+
+ eqcr_pi = s->eqcr.pi;
+ num_enqueued = (s->eqcr.available < num_frames) ?
+ s->eqcr.available : num_frames;
+ s->eqcr.available -= num_enqueued;
+ /* Fill in the EQCR ring */
+ for (i = 0; i < num_enqueued; i++) {
+ p = qbman_cena_write_start_wo_shadow(&s->sys,
+ QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
+ memcpy(&p[1], &cl[1], 28);
+ memcpy(&p[8], &fd[i], sizeof(*fd));
+ eqcr_pi++;
+ eqcr_pi &= 0xF;
+ /*Pointing to the next enqueue descriptor*/
+ cl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));
+ }
+
+ lwsync();
+
+ /* Set the verb byte, have to substitute in the valid-bit */
+ eqcr_pi = s->eqcr.pi;
+ cl = qb_cl(d);
+ for (i = 0; i < num_enqueued; i++) {
+ p = qbman_cena_write_start_wo_shadow(&s->sys,
+ QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
+ p[0] = cl[0] | s->eqcr.pi_vb;
+ eqcr_pi++;
+ eqcr_pi &= 0xF;
+ if (!(eqcr_pi & 7))
+ s->eqcr.pi_vb ^= QB_VALID_BIT;
+ /*Pointing to the next enqueue descriptor*/
+ cl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));
+ }
+
+ /* Flush all the cacheline without load/store in between */
+ eqcr_pi = s->eqcr.pi;
+ addr_cena = (uint64_t)s->sys.addr_cena;
+ for (i = 0; i < num_enqueued; i++) {
+ dcbf((uint64_t *)(addr_cena +
+ QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ eqcr_pi++;
+ eqcr_pi &= 0xF;
+ }
+ s->eqcr.pi = eqcr_pi;
+
+ return num_enqueued;
+}
+
/*************************/
/* Static (push) dequeue */
/*************************/
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 79cb648..7dd28da 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -66,6 +66,7 @@ DPDK_17.08 {
qbman_result_DQ_fqd_ctx;
qbman_swp_dqrr_consume;
qbman_swp_dqrr_next;
+ qbman_swp_enqueue_multiple_eqdesc;
qbman_swp_push_set;
rte_dpaa2_alloc_dpci_dev;
rte_fslmc_object_register;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 14/20] bus/fslmc: add callback per queue to enable
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (12 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 13/20] bus/fslmc: support enqueue with multiple enqueue descriptors Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 15/20] bus/fslmc: change func argument to const to avoid warning Nipun Gupta
` (6 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Dequeue from event device needs to process the event on
the basis of the hardware queue from which it is dequeued.
A callback is added into dpaa2_queue structure, to enable
event dequeue functionality to call that processing routine.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 9f9df50..119cf91 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -34,6 +34,8 @@
#ifndef _DPAA2_HW_PVT_H_
#define _DPAA2_HW_PVT_H_
+#include <rte_eventdev.h>
+
#include <mc/fsl_mc_sys.h>
#include <fsl_qbman_portal.h>
@@ -97,6 +99,8 @@ struct dpaa2_dpio_dev {
uintptr_t ci_size; /**< Size of the CI region */
int32_t vfio_fd; /**< File descriptor received via VFIO */
int32_t hw_id; /**< An unique ID of this DPIO device instance */
+ uint64_t dqrr_held;
+ uint8_t dqrr_size;
};
struct dpaa2_dpbp_dev {
@@ -112,6 +116,11 @@ struct queue_storage_info_t {
struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
};
+typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
+ const struct qbman_fd *fd,
+ const struct qbman_result *dq,
+ struct rte_event *ev);
+
struct dpaa2_queue {
struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
void *dev;
@@ -123,6 +132,7 @@ struct dpaa2_queue {
uint64_t tx_pkts;
uint64_t err_pkts;
struct queue_storage_info_t *q_storage;
+ dpaa2_queue_cb_dqrr_t *cb;
};
struct dpaa2_dpci_dev {
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 15/20] bus/fslmc: change func argument to const to avoid warning
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (13 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 14/20] bus/fslmc: add callback per queue to enable Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 16/20] event/dpaa2: add enqueue and dequeue functionality Nipun Gupta
` (5 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
qbman_get_dqrr_idx() API is required with constant dqrr entry
in the eventdev driver. Also, this routine is not updating the
dqrr. So, this patch updates its input argument to a const type.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 2 +-
drivers/bus/fslmc/qbman/qbman_portal.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
index 39407c8..06bd063 100644
--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
@@ -349,7 +349,7 @@ void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
*
* Return dqrr index.
*/
-uint8_t qbman_get_dqrr_idx(struct qbman_result *dqrr);
+uint8_t qbman_get_dqrr_idx(const struct qbman_result *dqrr);
/**
* qbman_get_dqrr_from_idx() - Use index to get the dqrr entry from the
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index 3f1b31d..e201a34 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -1463,7 +1463,7 @@ int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
1, ctx);
}
-uint8_t qbman_get_dqrr_idx(struct qbman_result *dqrr)
+uint8_t qbman_get_dqrr_idx(const struct qbman_result *dqrr)
{
return QBMAN_IDX_FROM_DQRR(dqrr);
}
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 16/20] event/dpaa2: add enqueue and dequeue functionality
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (14 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 15/20] bus/fslmc: change func argument to const to avoid warning Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 17/20] fslmc/bus: add interrupt enabling routine Nipun Gupta
` (4 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/event/dpaa2/dpaa2_eventdev.c | 170 +++++++++++++++++++++++++++++++++--
1 file changed, 163 insertions(+), 7 deletions(-)
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index cfb52bb..3f3e4a6 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -53,6 +53,7 @@
#include <rte_vdev.h>
#include <rte_fslmc.h>
#include <rte_atomic.h>
+#include <rte_memcpy.h>
#include <fslmc_vfio.h>
#include <dpaa2_hw_pvt.h>
@@ -74,11 +75,85 @@
dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
uint16_t nb_events)
{
+ struct rte_eventdev *ev_dev =
+ ((struct dpaa2_io_portal_t *)port)->eventdev;
+ struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
+ uint32_t queue_id = ev[0].queue_id;
+ struct evq_info_t *evq_info = &priv->evq_info[queue_id];
+ uint32_t fqid;
+ struct qbman_swp *swp;
+ struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
+ uint32_t loop, frames_to_send;
+ struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
+ uint16_t num_tx = 0;
+ int ret;
+
RTE_SET_USED(port);
- RTE_SET_USED(ev);
- RTE_SET_USED(nb_events);
- return 0;
+ if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
+ ret = dpaa2_affine_qbman_swp();
+ if (ret) {
+ PMD_DRV_LOG(ERR, PMD, "Failure in affining portal\n");
+ return 0;
+ }
+ }
+
+ swp = DPAA2_PER_LCORE_PORTAL;
+
+ while (nb_events) {
+ frames_to_send = (nb_events >> 3) ?
+ MAX_TX_RING_SLOTS : nb_events;
+
+ for (loop = 0; loop < frames_to_send; loop++) {
+ const struct rte_event *event = &ev[num_tx + loop];
+
+ if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
+ fqid = evq_info->dpci->queue[
+ DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
+ else
+ fqid = evq_info->dpci->queue[
+ DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
+
+ /* Prepare enqueue descriptor */
+ qbman_eq_desc_clear(&eqdesc[loop]);
+ qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
+ qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
+ qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
+
+ if (event->impl_opaque) {
+ uint8_t dqrr_index = event->impl_opaque - 1;
+
+ qbman_eq_desc_set_dca(&eqdesc[loop], 1,
+ dqrr_index, 0);
+ DPAA2_PER_LCORE_DPIO->dqrr_size--;
+ DPAA2_PER_LCORE_DPIO->dqrr_held &=
+ ~(1 << dqrr_index);
+ }
+
+ memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
+
+ /*
+ * todo - need to align with hw context data
+ * to avoid copy
+ */
+ struct rte_event *ev_temp = rte_malloc(NULL,
+ sizeof(struct rte_event), 0);
+ rte_memcpy(ev_temp, event, sizeof(struct rte_event));
+ DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
+ DPAA2_SET_FD_LEN((&fd_arr[loop]),
+ sizeof(struct rte_event));
+ }
+ loop = 0;
+ while (loop < frames_to_send) {
+ loop += qbman_swp_enqueue_multiple_eqdesc(swp,
+ &eqdesc[loop], &fd_arr[loop],
+ frames_to_send - loop);
+ }
+ num_tx += frames_to_send;
+ nb_events -= frames_to_send;
+ }
+
+ return num_tx;
}
static uint16_t
@@ -87,16 +162,91 @@
return dpaa2_eventdev_enqueue_burst(port, ev, 1);
}
+static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
+ const struct qbman_fd *fd,
+ const struct qbman_result *dq,
+ struct rte_event *ev)
+{
+ struct rte_event *ev_temp =
+ (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
+ rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
+ rte_free(ev_temp);
+
+ qbman_swp_dqrr_consume(swp, dq);
+}
+
+static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
+ const struct qbman_fd *fd,
+ const struct qbman_result *dq,
+ struct rte_event *ev)
+{
+ struct rte_event *ev_temp =
+ (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
+ uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
+
+ RTE_SET_USED(swp);
+
+ rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
+ rte_free(ev_temp);
+ ev->impl_opaque = dqrr_index + 1;
+ DPAA2_PER_LCORE_DPIO->dqrr_size++;
+ DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
+}
+
static uint16_t
dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
uint16_t nb_events, uint64_t timeout_ticks)
{
+ const struct qbman_result *dq;
+ struct qbman_swp *swp;
+ const struct qbman_fd *fd;
+ struct dpaa2_queue *rxq;
+ int num_pkts = 0, ret, i = 0;
+
RTE_SET_USED(port);
- RTE_SET_USED(ev);
- RTE_SET_USED(nb_events);
RTE_SET_USED(timeout_ticks);
- return 0;
+ if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
+ ret = dpaa2_affine_qbman_swp();
+ if (ret) {
+ PMD_DRV_LOG(ERR, PMD, "Failure in affining portal\n");
+ return 0;
+ }
+ }
+
+ swp = DPAA2_PER_LCORE_PORTAL;
+
+ /* Check if there are atomic contexts to be released */
+ while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
+ if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
+ dq = qbman_get_dqrr_from_idx(swp, i);
+ qbman_swp_dqrr_consume(swp, dq);
+ DPAA2_PER_LCORE_DPIO->dqrr_size--;
+ }
+ i++;
+ }
+ DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
+
+ do {
+ dq = qbman_swp_dqrr_next(swp);
+ if (!dq)
+ return 0;
+
+ fd = qbman_result_DQ_fd(dq);
+
+ rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
+ if (rxq) {
+ rxq->cb(swp, fd, dq, &ev[num_pkts]);
+ } else {
+ qbman_swp_dqrr_consume(swp, dq);
+ PMD_DRV_LOG(ERR, PMD, "Null Return VQ received\n");
+ return 0;
+ }
+
+ num_pkts++;
+ } while (num_pkts < nb_events);
+
+ return num_pkts;
}
static uint16_t
@@ -397,11 +547,17 @@
int ret, i;
/*Do settings to get the frame on a DPCON object*/
- rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST;
+ rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
+ DPCI_QUEUE_OPT_USER_CTX;
rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
+ dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
+ dpaa2_eventdev_process_parallel;
+ dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
+ dpaa2_eventdev_process_atomic;
+
for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
ret = dpci_set_rx_queue(&dpci_dev->dpci,
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 17/20] fslmc/bus: add interrupt enabling routine
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (15 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 16/20] event/dpaa2: add enqueue and dequeue functionality Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 18/20] bus/fslmc: enable portal interrupt handling Nipun Gupta
` (3 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 34 ++++++++++++++++++++++++++++++++++
drivers/bus/fslmc/fslmc_vfio.h | 3 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 07a9278..88cac20 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -362,6 +362,40 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
}
}
+#define IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + sizeof(int))
+
+int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle,
+ uint32_t index)
+{
+ struct vfio_irq_set *irq_set;
+ char irq_set_buf[IRQ_SET_BUF_LEN];
+ int *fd_ptr, fd, ret;
+
+ /* Prepare vfio_irq_set structure and SET the IRQ in VFIO */
+ /* Give the eventfd to VFIO */
+ fd = eventfd(0, 0);
+ irq_set = (struct vfio_irq_set *)irq_set_buf;
+ irq_set->argsz = sizeof(irq_set_buf);
+ irq_set->count = 1;
+ irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
+ VFIO_IRQ_SET_ACTION_TRIGGER;
+ irq_set->index = index;
+ irq_set->start = 0;
+ fd_ptr = (int *)&irq_set->data;
+ *fd_ptr = fd;
+
+ ret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ if (ret < 0) {
+ FSLMC_VFIO_LOG(ERR, "Unable to set IRQ in VFIO, ret: %d\n",
+ ret);
+ return -1;
+ }
+
+ /* Set the FD and update the flags */
+ intr_handle->fd = fd;
+ return 0;
+}
+
/* Following function shall fetch total available list of MC devices
* from VFIO container & populate private list of devices and other
* data structures
diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h
index 7c725f4..ebca2b0 100644
--- a/drivers/bus/fslmc/fslmc_vfio.h
+++ b/drivers/bus/fslmc/fslmc_vfio.h
@@ -90,6 +90,9 @@ int vfio_dmamap_mem_region(
uint64_t iova,
uint64_t size);
+int rte_dpaa2_intr_enable(struct rte_intr_handle *intr_handle,
+ uint32_t index);
+
int fslmc_vfio_setup_group(void);
int fslmc_vfio_process_group(void);
int rte_fslmc_vfio_dmamap(void);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 18/20] bus/fslmc: enable portal interrupt handling
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (16 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 17/20] fslmc/bus: add interrupt enabling routine Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-25 18:07 ` [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue Nipun Gupta
` (2 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Eventdev requires portal interrupts to handle timeout in the
event dequeue. This patch provides mechanism to enable the
portal interrupts.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 108 ++++++++++++++++++++-
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 3 +-
drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 30 ++++++
drivers/bus/fslmc/qbman/qbman_portal.c | 22 +++++
drivers/bus/fslmc/rte_bus_fslmc_version.map | 1 +
5 files changed, 158 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index f88d490..babc2f9 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -46,6 +46,8 @@
#include <sys/stat.h>
#include <sys/mman.h>
#include <sys/syscall.h>
+#include <sys/epoll.h>
+#include<sys/eventfd.h>
#include <rte_mbuf.h>
#include <rte_ethdev.h>
@@ -102,6 +104,95 @@
return dpaa2_core_cluster_base + x;
}
+static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
+{
+#define STRING_LEN 28
+#define COMMAND_LEN 50
+ uint32_t cpu_mask = 1;
+ int ret;
+ size_t len = 0;
+ char *temp = NULL, *token = NULL;
+ char string[STRING_LEN], command[COMMAND_LEN];
+ FILE *file;
+
+ snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
+ file = fopen("/proc/interrupts", "r");
+ if (!file) {
+ PMD_DRV_LOG(WARN, "Failed to open /proc/interrupts file\n");
+ return;
+ }
+ while (getline(&temp, &len, file) != -1) {
+ if ((strstr(temp, string)) != NULL) {
+ token = strtok(temp, ":");
+ break;
+ }
+ }
+
+ if (!token) {
+ PMD_DRV_LOG(WARN, "Failed to get interrupt id for dpio.%d\n",
+ dpio_id);
+ if (temp)
+ free(temp);
+ fclose(file);
+ return;
+ }
+
+ cpu_mask = cpu_mask << rte_lcore_id();
+ snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
+ cpu_mask, token);
+ ret = system(command);
+ if (ret < 0)
+ PMD_DRV_LOG(WARN,
+ "Failed to affine interrupts on respective core\n");
+ else
+ PMD_DRV_LOG(WARN, " %s command is executed\n", command);
+
+ free(temp);
+ fclose(file);
+}
+
+static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
+{
+ struct epoll_event epoll_ev;
+ int eventfd, dpio_epoll_fd, ret;
+ int threshold = 0x3, timeout = 0xFF;
+
+ dpio_epoll_fd = epoll_create(1);
+ ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
+ if (ret) {
+ PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
+ return -1;
+ }
+
+ if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
+ threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
+
+ if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
+ sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
+
+ qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
+ QBMAN_SWP_INTERRUPT_DQRI);
+ qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
+ qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
+ qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
+ qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
+
+ eventfd = dpio_dev->intr_handle.fd;
+ epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
+ epoll_ev.data.fd = eventfd;
+
+ ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
+ return -1;
+ }
+ dpio_dev->epoll_fd = dpio_epoll_fd;
+
+ dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
+
+ return 0;
+}
+
static int
configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
{
@@ -201,6 +292,11 @@
return -1;
}
+ if (dpaa2_dpio_intr_init(dpio_dev)) {
+ PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
+ return -1;
+ }
+
return 0;
}
@@ -325,6 +421,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
{
struct dpaa2_dpio_dev *dpio_dev;
struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
+ int vfio_dev_fd;
if (obj_info->num_regions < NUM_DPIO_REGIONS) {
PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
@@ -352,13 +449,14 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev);
dpio_dev->dpio = NULL;
dpio_dev->hw_id = object_id;
- dpio_dev->vfio_fd = vdev->fd;
+ dpio_dev->intr_handle.vfio_dev_fd = vdev->fd;
rte_atomic16_init(&dpio_dev->ref_count);
/* Using single portal for all devices */
dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
reg_info.index = 0;
- if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
+ vfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd;
+ if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
free(dpio_dev);
return -1;
@@ -369,7 +467,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
dpio_dev->ce_size = reg_info.size;
dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
- dpio_dev->vfio_fd, reg_info.offset);
+ vfio_dev_fd, reg_info.offset);
/* Create Mapping for QBMan Cache Enabled area. This is a fix for
* SMMU fault for DQRR statshing transaction.
@@ -382,7 +480,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
}
reg_info.index = 1;
- if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
+ if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
free(dpio_dev);
return -1;
@@ -393,7 +491,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
dpio_dev->ci_size = reg_info.size;
dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
- dpio_dev->vfio_fd, reg_info.offset);
+ vfio_dev_fd, reg_info.offset);
if (configure_dpio_qbman_swp(dpio_dev)) {
PMD_INIT_LOG(ERR,
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 119cf91..f1d7735 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -97,7 +97,8 @@ struct dpaa2_dpio_dev {
uintptr_t qbman_portal_ci_paddr;
/**< Physical address of Cache Inhibit Area */
uintptr_t ci_size; /**< Size of the CI region */
- int32_t vfio_fd; /**< File descriptor received via VFIO */
+ struct rte_intr_handle intr_handle; /* Interrupt related info */
+ int32_t epoll_fd; /**< File descriptor created for interrupt polling */
int32_t hw_id; /**< An unique ID of this DPIO device instance */
uint64_t dqrr_held;
uint8_t dqrr_size;
diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
index 06bd063..9e9047e 100644
--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h
@@ -124,6 +124,36 @@
void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask);
/**
+ * qbman_swp_dqrr_thrshld_read_status() - Get the data in software portal
+ * DQRR interrupt threshold register.
+ * @p: the given software portal object.
+ */
+uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p);
+
+/**
+ * qbman_swp_dqrr_thrshld_write() - Set the data in software portal
+ * DQRR interrupt threshold register.
+ * @p: the given software portal object.
+ * @mask: The value to set in SWP_DQRR_ITR register.
+ */
+void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask);
+
+/**
+ * qbman_swp_intr_timeout_read_status() - Get the data in software portal
+ * Interrupt Time-Out period register.
+ * @p: the given software portal object.
+ */
+uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p);
+
+/**
+ * qbman_swp_intr_timeout_write() - Set the data in software portal
+ * Interrupt Time-Out period register.
+ * @p: the given software portal object.
+ * @mask: The value to set in SWP_ITPR register.
+ */
+void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask);
+
+/**
* qbman_swp_interrupt_get_trigger() - Get the data in software portal
* interrupt enable register.
* @p: the given software portal object.
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index e201a34..244c0cf 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -44,6 +44,8 @@
#define QBMAN_CINH_SWP_IER 0xe40
#define QBMAN_CINH_SWP_ISDR 0xe80
#define QBMAN_CINH_SWP_IIR 0xec0
+#define QBMAN_CINH_SWP_DQRR_ITR 0xa80
+#define QBMAN_CINH_SWP_ITPR 0xf40
/* CENA register offsets */
#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
@@ -218,6 +220,26 @@ void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)
qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);
}
+uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p)
+{
+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQRR_ITR);
+}
+
+void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask)
+{
+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_DQRR_ITR, mask);
+}
+
+uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p)
+{
+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ITPR);
+}
+
+void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask)
+{
+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ITPR, mask);
+}
+
uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
{
return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);
diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map
index 7dd28da..78671a8 100644
--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map
+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map
@@ -67,6 +67,7 @@ DPDK_17.08 {
qbman_swp_dqrr_consume;
qbman_swp_dqrr_next;
qbman_swp_enqueue_multiple_eqdesc;
+ qbman_swp_interrupt_clear_status;
qbman_swp_push_set;
rte_dpaa2_alloc_dpci_dev;
rte_fslmc_object_register;
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (17 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 18/20] bus/fslmc: enable portal interrupt handling Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-31 15:49 ` Jerin Jacob
2017-05-25 18:07 ` [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details Nipun Gupta
2017-05-31 14:50 ` [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Jerin Jacob
20 siblings, 1 reply; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
This patch adds support for interrupt handling on the event port.
These interrupts facilitates managing of timeout ticks in the
event dequeue functions.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/event/dpaa2/dpaa2_eventdev.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index 3f3e4a6..a24b751 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -162,6 +162,31 @@
return dpaa2_eventdev_enqueue_burst(port, ev, 1);
}
+static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
+{
+ struct epoll_event epoll_ev;
+ int ret, i = 0;
+
+ qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
+ QBMAN_SWP_INTERRUPT_DQRI);
+
+RETRY:
+ ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
+ &epoll_ev, 1, timeout_ticks);
+ if (ret < 1) {
+ /* sometimes due to some spurious interrupts epoll_wait fails
+ with errno EINTR. so here we are retrying epoll_wait in such
+ case to avoid the problem.*/
+ if (errno == EINTR) {
+ PMD_DRV_LOG(DEBUG, PMD, "epoll_wait fails\n");
+ if (i++ > 10)
+ PMD_DRV_LOG(DEBUG, PMD,
+ "Dequeue burst Failed\n");
+ goto RETRY;
+ }
+ }
+}
+
static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
const struct qbman_fd *fd,
const struct qbman_result *dq,
@@ -204,7 +229,6 @@ static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
int num_pkts = 0, ret, i = 0;
RTE_SET_USED(port);
- RTE_SET_USED(timeout_ticks);
if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
ret = dpaa2_affine_qbman_swp();
@@ -229,8 +253,14 @@ static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
do {
dq = qbman_swp_dqrr_next(swp);
- if (!dq)
- return 0;
+ if (!dq) {
+ if (!num_pkts && timeout_ticks) {
+ dpaa2_eventdev_dequeue_wait(timeout_ticks);
+ timeout_ticks = 0;
+ continue;
+ }
+ return num_pkts;
+ }
fd = qbman_result_DQ_fd(dq);
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue
2017-05-25 18:07 ` [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue Nipun Gupta
@ 2017-05-31 15:49 ` Jerin Jacob
2017-06-01 11:42 ` Nipun Gupta
0 siblings, 1 reply; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 15:49 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:50 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 19/20] event/dpaa2: handle timeout using interrupts in
> dequeue
> X-Mailer: git-send-email 1.9.1
>
> This patch adds support for interrupt handling on the event port.
> These interrupts facilitates managing of timeout ticks in the
> event dequeue functions.
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Please check the check-patch errors.
http://dpdk.org/dev/patchwork/project/dpdk/list/?submitter=Nipun
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue
2017-05-31 15:49 ` Jerin Jacob
@ 2017-06-01 11:42 ` Nipun Gupta
0 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-06-01 11:42 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, Hemant Agrawal, harry.van.haaren, bruce.richardson,
gage.eads, Shreyansh Jain
> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Wednesday, May 31, 2017 21:19
> To: Nipun Gupta <nipun.gupta@nxp.com>
> Cc: dev@dpdk.org; Hemant Agrawal <hemant.agrawal@nxp.com>;
> harry.van.haaren@intel.com; bruce.richardson@intel.com;
> gage.eads@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>
> Subject: Re: [PATCH 19/20] event/dpaa2: handle timeout using interrupts in
> dequeue
>
> -----Original Message-----
> > Date: Thu, 25 May 2017 23:37:50 +0530
> > From: Nipun Gupta <nipun.gupta@nxp.com>
> > To: dev@dpdk.org
> > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > <nipun.gupta@nxp.com>
> > Subject: [PATCH 19/20] event/dpaa2: handle timeout using interrupts in
> > dequeue
> > X-Mailer: git-send-email 1.9.1
> >
> > This patch adds support for interrupt handling on the event port.
> > These interrupts facilitates managing of timeout ticks in the
> > event dequeue functions.
> >
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
>
> Please check the check-patch errors.
> http://dpdk.org/dev/patchwork/project/dpdk/list/?submitter=Nipun
Somehow they managed to peek in. Ill fix them in next version.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (18 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 19/20] event/dpaa2: handle timeout using interrupts in dequeue Nipun Gupta
@ 2017-05-25 18:07 ` Nipun Gupta
2017-05-31 15:58 ` Jerin Jacob
2017-05-31 14:50 ` [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Jerin Jacob
20 siblings, 1 reply; 34+ messages in thread
From: Nipun Gupta @ 2017-05-25 18:07 UTC (permalink / raw)
To: dev
Cc: hemant.agrawal, jerin.jacob, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, Nipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
MAINTAINERS | 1 +
doc/guides/eventdevs/dpaa2.rst | 157 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 doc/guides/eventdevs/dpaa2.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 45e284e..9c9095b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -584,6 +584,7 @@ NXP DPAA2 Eventdev PMD
M: Hemant Agrawal <hemant.agrawal@nxp.com>
M: Nipun Gupta <nipun.gupta@nxp.com>
F: drivers/event/dpaa2/
+F: doc/guides/eventdevs/dpaa2.rst
Packet processing
-----------------
diff --git a/doc/guides/eventdevs/dpaa2.rst b/doc/guides/eventdevs/dpaa2.rst
new file mode 100644
index 0000000..42453b2
--- /dev/null
+++ b/doc/guides/eventdevs/dpaa2.rst
@@ -0,0 +1,157 @@
+.. BSD LICENSE
+ Copyright 2017 NXP.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of NXP nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+NXP DPAA2 Eventdev Driver
+==================================
+
+The dpaa2 eventdev is an implementation of the eventdev API, that provides a
+wide range of the eventdev features. The eventdev relies on a dpaa2 hw to
+perform event scheduling.
+
+More information can be found at `NXP Official Website
+<http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-arm-processors:QORIQ-ARM>`_.
+
+Features
+--------
+
+The DPAA2 EVENTDEV implements many features in the eventdev API;
+
+- Hardware based event scheduler
+- 8 event ports
+- 8 event queues
+- Parallel flows
+- Atomic flows
+
+Supported DPAA2 SoCs
+--------------------
+
+- LS2080A/LS2040A
+- LS2084A/LS2044A
+- LS2088A/LS2048A
+- LS1088A/LS1048A
+
+Prerequisites
+-------------
+
+There are three main pre-requisities for executing DPAA2 EVENTDEV on a DPAA2
+compatible board:
+
+1. **ARM 64 Tool Chain**
+
+ For example, the `*aarch64* Linaro Toolchain <https://releases.linaro.org/components/toolchain/binaries/4.9-2017.01/aarch64-linux-gnu>`_.
+
+2. **Linux Kernel**
+
+ It can be obtained from `NXP's Github hosting <https://github.com/qoriq-open-source/linux>`_.
+
+3. **Rootfile system**
+
+ Any *aarch64* supporting filesystem can be used. For example,
+ Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained
+ from `here <http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz>`_.
+
+As an alternative method, DPAA2 EVENTDEV can also be executed using images provided
+as part of SDK from NXP. The SDK includes all the above prerequisites necessary
+to bring up a DPAA2 board.
+
+The following dependencies are not part of DPDK and must be installed
+separately:
+
+- **NXP Linux SDK**
+
+ NXP Linux software development kit (SDK) includes support for family
+ of QorIQ® ARM-Architecture-based system on chip (SoC) processors
+ and corresponding boards.
+
+ It includes the Linux board support packages (BSPs) for NXP SoCs,
+ a fully operational tool chain, kernel and board specific modules.
+
+ SDK and related information can be obtained from: `NXP QorIQ SDK <http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX>`_.
+
+- **DPDK Helper Scripts**
+
+ DPAA2 based resources can be configured easily with the help of ready scripts
+ as provided in the DPDK helper repository.
+
+ `DPDK Helper Scripts <https://github.com/qoriq-open-source/dpdk-helper>`_.
+
+Currently supported by DPDK:
+
+- NXP SDK **2.0+**.
+- MC Firmware version **10.0.0** and higher.
+- Supported architectures: **arm64 LE**.
+
+- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.
+
+.. note::
+
+ Some part of fslmc bus code (mc flib - object library) routines are
+ dual licensed (BSD & GPLv2).
+
+Pre-Installation Configuration
+------------------------------
+
+Config File Options
+~~~~~~~~~~~~~~~~~~~
+
+The following options can be modified in the ``config`` file.
+Please note that enabling debugging options may affect system performance.
+
+- ``CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV`` (default ``y``)
+
+ Toggle compilation of the ``lrte_pmd_dpaa2_event`` driver.
+
+- ``CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG`` (default ``n``)
+
+ Toggle display of generic debugging messages
+
+Driver Compilation
+~~~~~~~~~~~~~~~~~~
+
+To compile the DPAA2 EVENTDEV PMD for Linux arm64 gcc target, run the
+following ``make`` command:
+
+.. code-block:: console
+
+ cd <DPDK-source-directory>
+ make config T=arm64-dpaa2-linuxapp-gcc install
+
+Limitations
+-----------
+
+Platform Requirement
+~~~~~~~~~~~~~~~~~~~~
+
+DPAA2 drivers for DPDK can only work on NXP SoCs as listed in the
+``Supported DPAA2 SoCs``.
+
+Port-core binding
+~~~~~~~~~~~~~~~~~
+
+DPAA2 EVENTDEV driver requires event port 'x' to be used on core 'x'.
--
1.9.1
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
2017-05-25 18:07 ` [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details Nipun Gupta
@ 2017-05-31 15:58 ` Jerin Jacob
2017-06-01 12:07 ` Nipun Gupta
0 siblings, 1 reply; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 15:58 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:51 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
> X-Mailer: git-send-email 1.9.1
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> ---
> MAINTAINERS | 1 +
> doc/guides/eventdevs/dpaa2.rst | 157 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 158 insertions(+)
> create mode 100644 doc/guides/eventdevs/dpaa2.rst
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 45e284e..9c9095b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -584,6 +584,7 @@ NXP DPAA2 Eventdev PMD
> M: Hemant Agrawal <hemant.agrawal@nxp.com>
> M: Nipun Gupta <nipun.gupta@nxp.com>
> F: drivers/event/dpaa2/
> +F: doc/guides/eventdevs/dpaa2.rst
>
> Packet processing
> -----------------
> +
> +To compile the DPAA2 EVENTDEV PMD for Linux arm64 gcc target, run the
> +following ``make`` command:
> +
> +.. code-block:: console
> +
> + cd <DPDK-source-directory>
> + make config T=arm64-dpaa2-linuxapp-gcc install
It nice to mention your PMD driver vdev name in the document.
> +
> +Limitations
> +-----------
> +
> +Platform Requirement
> +~~~~~~~~~~~~~~~~~~~~
> +
> +DPAA2 drivers for DPDK can only work on NXP SoCs as listed in the
> +``Supported DPAA2 SoCs``.
> +
> +Port-core binding
> +~~~~~~~~~~~~~~~~~
> +
> +DPAA2 EVENTDEV driver requires event port 'x' to be used on core 'x'.
Is it a HW limitation? or Is it like, only one port can connect to one
lcore. If it latter, then I think, you can have physical port to virtual
port translation in slow path as ports are enumerated as 0 to N. lcore
id can be anything.
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
2017-05-31 15:58 ` Jerin Jacob
@ 2017-06-01 12:07 ` Nipun Gupta
0 siblings, 0 replies; 34+ messages in thread
From: Nipun Gupta @ 2017-06-01 12:07 UTC (permalink / raw)
To: Jerin Jacob
Cc: dev, Hemant Agrawal, harry.van.haaren, bruce.richardson,
gage.eads, Shreyansh Jain
> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Wednesday, May 31, 2017 21:28
> To: Nipun Gupta <nipun.gupta@nxp.com>
> Cc: dev@dpdk.org; Hemant Agrawal <hemant.agrawal@nxp.com>;
> harry.van.haaren@intel.com; bruce.richardson@intel.com;
> gage.eads@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>
> Subject: Re: [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
>
> -----Original Message-----
> > Date: Thu, 25 May 2017 23:37:51 +0530
> > From: Nipun Gupta <nipun.gupta@nxp.com>
> > To: dev@dpdk.org
> > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > <nipun.gupta@nxp.com>
> > Subject: [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details
> > X-Mailer: git-send-email 1.9.1
> >
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > ---
> > MAINTAINERS | 1 +
> > doc/guides/eventdevs/dpaa2.rst | 157
> +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 158 insertions(+)
> > create mode 100644 doc/guides/eventdevs/dpaa2.rst
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 45e284e..9c9095b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -584,6 +584,7 @@ NXP DPAA2 Eventdev PMD
> > M: Hemant Agrawal <hemant.agrawal@nxp.com>
> > M: Nipun Gupta <nipun.gupta@nxp.com>
> > F: drivers/event/dpaa2/
> > +F: doc/guides/eventdevs/dpaa2.rst
> >
> > Packet processing
> > -----------------
> > +
> > +To compile the DPAA2 EVENTDEV PMD for Linux arm64 gcc target, run the
> > +following ``make`` command:
> > +
> > +.. code-block:: console
> > +
> > + cd <DPDK-source-directory>
> > + make config T=arm64-dpaa2-linuxapp-gcc install
>
> It nice to mention your PMD driver vdev name in the document.
>
> > +
> > +Limitations
> > +-----------
> > +
> > +Platform Requirement
> > +~~~~~~~~~~~~~~~~~~~~
> > +
> > +DPAA2 drivers for DPDK can only work on NXP SoCs as listed in the
> > +``Supported DPAA2 SoCs``.
> > +
> > +Port-core binding
> > +~~~~~~~~~~~~~~~~~
> > +
> > +DPAA2 EVENTDEV driver requires event port 'x' to be used on core 'x'.
>
> Is it a HW limitation? or Is it like, only one port can connect to one
> lcore. If it latter, then I think, you can have physical port to virtual
> port translation in slow path as ports are enumerated as 0 to N. lcore
> id can be anything.
Appreciate your suggestion, but right now our event driver limits this.
This is because core needs to be known at event port setup.
As event port setup is done at initialization time, we need to have this limitation.
We are having discussions to somehow do away with this.
Thanks,
Nipun
>
>
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD
2017-05-25 18:07 [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Nipun Gupta
` (19 preceding siblings ...)
2017-05-25 18:07 ` [dpdk-dev] [PATCH 20/20] doc: add NXP DPAA2 EVENTDEV details Nipun Gupta
@ 2017-05-31 14:50 ` Jerin Jacob
2017-05-31 16:17 ` Thomas Monjalon
20 siblings, 1 reply; 34+ messages in thread
From: Jerin Jacob @ 2017-05-31 14:50 UTC (permalink / raw)
To: Nipun Gupta
Cc: dev, hemant.agrawal, harry.van.haaren, bruce.richardson,
gage.eads, shreyansh.jain, thomas
-----Original Message-----
> Date: Thu, 25 May 2017 23:37:31 +0530
> From: Nipun Gupta <nipun.gupta@nxp.com>
> To: dev@dpdk.org
> CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> harry.van.haaren@intel.com, bruce.richardson@intel.com,
> gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> <nipun.gupta@nxp.com>
> Subject: [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD
> X-Mailer: git-send-email 1.9.1
>
> The following patch set adds NXP DPAA2 HW based eventdev
> implementation to the next-eventdev tree.
>
> The patchset consists of the following:
> - DPCON support required by DPAA2 eventdev
> - DPCI support in fslmc bus
> - Interrupt support in QBMAN
> - Implemetation of eventdev API's for DPAA2
> - Documentation of DPAA2 eventdev PMD
>
> Hemant Agrawal (2):
> bus/fslmc: generic framework for mc object creation
> bus/fslmc: export qbman dqrr funcs for eventdev usages
>
> Nipun Gupta (18):
> event/dpaa2: add basic build infrastructure
> bus/fslmc: integrating dpio and dpbp to object framework
> bus/fslmc: adding basic dpcon support
> event/dpaa2: register dpcon as dpaa2 device for bus scan
> bus/fslmc: adding basic dpci support
> bus/fslmc: register dpci as dpaa2 device for bus scan
> bus/fslmc: adding cpu support in stashing config
Thomas,
Is it OK to take bus/ related changes through eventdev-next?
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD
2017-05-31 14:50 ` [dpdk-dev] [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD Jerin Jacob
@ 2017-05-31 16:17 ` Thomas Monjalon
0 siblings, 0 replies; 34+ messages in thread
From: Thomas Monjalon @ 2017-05-31 16:17 UTC (permalink / raw)
To: Jerin Jacob
Cc: Nipun Gupta, dev, hemant.agrawal, harry.van.haaren,
bruce.richardson, gage.eads, shreyansh.jain
31/05/2017 16:50, Jerin Jacob:
> -----Original Message-----
> > Date: Thu, 25 May 2017 23:37:31 +0530
> > From: Nipun Gupta <nipun.gupta@nxp.com>
> > To: dev@dpdk.org
> > CC: hemant.agrawal@nxp.com, jerin.jacob@caviumnetworks.com,
> > harry.van.haaren@intel.com, bruce.richardson@intel.com,
> > gage.eads@intel.com, shreyansh.jain@nxp.com, Nipun Gupta
> > <nipun.gupta@nxp.com>
> > Subject: [PATCH 00/20] next-eventdev: NXP DPAA2 eventdev PMD
> > X-Mailer: git-send-email 1.9.1
> >
> > The following patch set adds NXP DPAA2 HW based eventdev
> > implementation to the next-eventdev tree.
> >
> > The patchset consists of the following:
> > - DPCON support required by DPAA2 eventdev
> > - DPCI support in fslmc bus
> > - Interrupt support in QBMAN
> > - Implemetation of eventdev API's for DPAA2
> > - Documentation of DPAA2 eventdev PMD
> >
> > Hemant Agrawal (2):
> > bus/fslmc: generic framework for mc object creation
> > bus/fslmc: export qbman dqrr funcs for eventdev usages
> >
> > Nipun Gupta (18):
> > event/dpaa2: add basic build infrastructure
> > bus/fslmc: integrating dpio and dpbp to object framework
> > bus/fslmc: adding basic dpcon support
> > event/dpaa2: register dpcon as dpaa2 device for bus scan
> > bus/fslmc: adding basic dpci support
> > bus/fslmc: register dpci as dpaa2 device for bus scan
> > bus/fslmc: adding cpu support in stashing config
>
> Thomas,
> Is it OK to take bus/ related changes through eventdev-next?
Yes if it is only related to eventdev.
We must take care that these changes won't be needed by next-net,
otherwise it must go in master branch.
^ permalink raw reply [flat|nested] 34+ messages in thread