From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 1901B2C1A for ; Tue, 6 Jun 2017 14:42:17 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2017 05:42:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,306,1493708400"; d="scan'208";a="96129879" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.28]) by orsmga002.jf.intel.com with SMTP; 06 Jun 2017 05:42:02 -0700 Received: by (sSMTP sendmail emulation); Tue, 06 Jun 2017 13:42:01 +0100 Date: Tue, 6 Jun 2017 13:42:01 +0100 From: Bruce Richardson To: "Ananyev, Konstantin" Cc: "Verkamp, Daniel" , "dev@dpdk.org" Message-ID: <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> References: <20170602200337.50743-1-daniel.verkamp@intel.com> <20170602201213.51143-1-daniel.verkamp@intel.com> <2601191342CEEE43887BDE71AB9772583FB05190@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB05216@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.8.1 (2017-04-11) Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jun 2017 12:42:18 -0000 On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konstantin wrote: > > > > > > > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so members > > > of struct rte_ring are 128 byte aligned, > > > >and therefore the whole struct needs 128-byte alignment according to the ABI > > > so that the 128-byte alignment of the fields can be guaranteed. > > > > > > Ah ok, missed the fact that rte_ring is 128B aligned these days. > > > BTW, I probably missed the initial discussion, but what was the reason for that? > > > Konstantin > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems unnecessary if the cache line is only 64 bytes. An alternate > > fix would be to just use cache line alignment for these fields (since memzones are already cache line aligned). > > Yes, had the same thought. > > > Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h? > > Might be, would be good to hear opinion the author of that change. It gives improved performance for core-2-core transfer. /Bruce