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From: Olivier Matz <olivier.matz@6wind.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Cc: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
	"Verkamp, Daniel" <daniel.verkamp@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
Date: Thu, 8 Jun 2017 14:45:40 +0200	[thread overview]
Message-ID: <20170608144540.5a8e3603@platinum> (raw)
In-Reply-To: <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com>

On Tue, 6 Jun 2017 15:56:28 +0100, Bruce Richardson <bruce.richardson@intel.com> wrote:
> On Tue, Jun 06, 2017 at 02:19:21PM +0100, Ananyev, Konstantin wrote:
> > 
> >   
> > > -----Original Message-----
> > > From: Richardson, Bruce
> > > Sent: Tuesday, June 6, 2017 1:42 PM
> > > To: Ananyev, Konstantin <konstantin.ananyev@intel.com>
> > > Cc: Verkamp, Daniel <daniel.verkamp@intel.com>; dev@dpdk.org
> > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> > > 
> > > On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konstantin wrote:  
> > > >  
> > > > > >
> > > > > >
> > > > > >  
> > > > > > >
> > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so members  
> > > > > > of struct rte_ring are 128 byte aligned,  
> > > > > > >and therefore the whole struct needs 128-byte alignment according to the ABI  
> > > > > > so that the 128-byte alignment of the fields can be guaranteed.
> > > > > >
> > > > > > Ah ok, missed the fact that rte_ring is 128B aligned these days.
> > > > > > BTW, I probably missed the initial discussion, but what was the reason for that?
> > > > > > Konstantin  
> > > > >
> > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems unnecessary if the cache line is only 64 bytes.  An  
> > > alternate  
> > > > > fix would be to just use cache line alignment for these fields (since memzones are already cache line aligned).  
> > > >
> > > > Yes, had the same thought.
> > > >  
> > > > > Maybe there is some deeper  reason for the >= 128-byte alignment logic in rte_ring.h?  
> > > >
> > > > Might be, would be good to hear opinion the author of that change.  
> > > 
> > > It gives improved performance for core-2-core transfer.  
> > 
> > You mean empty cache-line(s) after prod/cons, correct?
> > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries?
> > Something like that:
> > struct rte_ring {
> >    ...
> >    struct rte_ring_headtail prod __rte_cache_aligned;
> >    EMPTY_CACHE_LINE   __rte_cache_aligned;
> >    struct rte_ring_headtail cons __rte_cache_aligned;
> >    EMPTY_CACHE_LINE   __rte_cache_aligned;
> > };
> > 
> > Konstantin  
> 
> Sure. That should probably work too. 
> 
> /Bruce

I also agree with Konstantin's proposal. One question though: since it
changes the alignment constraint of the rte_ring structure, I think it is
an ABI breakage: a structure including the rte_ring structure inherits
from this constraint.

How could we handle that, knowing this is probably a rare case?

  reply	other threads:[~2017-06-08 12:45 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-02 20:03 [dpdk-dev] [PATCH] " Daniel Verkamp
2017-06-02 20:12 ` [dpdk-dev] [PATCH v2] " Daniel Verkamp
2017-06-02 20:51   ` Ananyev, Konstantin
2017-06-02 22:24     ` Verkamp, Daniel
2017-06-03 10:00       ` Ananyev, Konstantin
2017-06-05 16:21         ` Verkamp, Daniel
2017-06-06  9:59           ` Ananyev, Konstantin
2017-06-06 12:42             ` Bruce Richardson
2017-06-06 13:19               ` Ananyev, Konstantin
2017-06-06 14:56                 ` Bruce Richardson
2017-06-08 12:45                   ` Olivier Matz [this message]
2017-06-08 13:20                     ` Bruce Richardson
2017-06-08 14:05                       ` Olivier Matz
2017-06-08 14:11                         ` Bruce Richardson
2017-06-08 14:50                           ` Ananyev, Konstantin
2017-06-08 15:24                             ` Bruce Richardson
2017-06-08 15:35                               ` Ananyev, Konstantin
2017-06-08 16:03                                 ` Bruce Richardson
2017-06-08 16:12                                   ` Ananyev, Konstantin
2017-06-08 16:20                                     ` Richardson, Bruce
2017-06-08 16:42                                       ` Ananyev, Konstantin
2017-06-09  9:02                                         ` Bruce Richardson
2017-06-12  9:02                                           ` Olivier Matz
2017-06-12  9:56                                             ` Bruce Richardson
2017-06-30 11:35                                               ` Olivier Matz
2017-06-09 12:47                 ` Yerden Zhumabekov
2017-06-09 17:16                   ` Stephen Hemminger
2017-06-09 17:28                     ` Jerin Jacob
2017-06-10  8:16                       ` Ananyev, Konstantin
2017-06-12  3:07                         ` Jerin Jacob
2017-06-12 10:18                           ` Ananyev, Konstantin
2017-06-12 10:34                             ` Jerin Jacob
2017-06-12 11:09                               ` Bruce Richardson
2017-06-12 11:41                                 ` Jerin Jacob
2017-06-12 12:17                                   ` Ananyev, Konstantin
2017-06-12 12:42                                     ` Jerin Jacob
2017-06-12 12:51                                       ` Ananyev, Konstantin
2017-06-12 13:06                                         ` Bruce Richardson
2017-06-12 13:20                                         ` Jerin Jacob
2017-06-30 11:36   ` Olivier Matz
2017-07-01 11:14     ` Thomas Monjalon
2017-07-01 11:25       ` Thomas Monjalon

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