From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by dpdk.org (Postfix) with ESMTP id 0E2A22BA1 for ; Thu, 8 Jun 2017 14:45:43 +0200 (CEST) Received: by mail-wm0-f52.google.com with SMTP id x70so76729232wme.0 for ; Thu, 08 Jun 2017 05:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WgPudGTJyJtnuvYVGehIYAK2HGMhZefzAmLf0ER7nbg=; b=Ou0eG3LkQm8bhqLGL9u43f+2aQfvWHFogUOQnauDl0OPPu3V1ombQwsl+XfXPgPFcJ OIykf2seiGHC8u6tkQhWLNVaES8Jzq/5VB4g4az1ihQwxTDHsGDyeUvyxKjFRneK5iC5 1deZ1Vi9MV2tFwAO3XO3uJ79J5O0Hy4yFQaIfNk0/qDPTvKAhchruN/uBun6wdRDRNVJ /D23j7WkkKEo7bam5yM10r3DTSuelgu95YcnTjiA4O9rBY/j8b2VW10Crf+GMP9ylzKm NLE33o106UEa0jpJx8oZYWTggFTg77aU4F8snhMJ6AC4N9t25Qjj/IpvWf8gHC96ne8K aPeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WgPudGTJyJtnuvYVGehIYAK2HGMhZefzAmLf0ER7nbg=; b=qRPPr6A8HSAApbSrMbkNbllkXTa/oA9sR32VwRbJYqgoX/4KkdG8sDdAKoaci7bHms pxCC/A1nFJimnxsrDjGLFheP8hw8pH3vE/LMLDoyau0gxiDUpzc3Zu58Dbe3ntjJAtO2 wG07yEV1lWiCnwIqJoLI9nH7SwlF3lYOGZan6R0AlptlnCViW+mJV/4mk7zbAIwjy2wI ICwrDVp69U/rtUMDzE3UNlQ8g2B+/0ls+SdPLqTnJgYV9qeHfP8ncM2Xak9OUH2N+XSb 5deMQKinMDqqx6lyCVHYYVBUd3HEoZMVdwXMiXT4vNoBLBEfCTy+C+wqcuMHq3a3mLyq WlMw== X-Gm-Message-State: AODbwcCwE+pFdWDkkf/R7xuOD4+GGbbBMUsY2DBYM6VnMjDv/MpFT2tP ijlEblhzqQ0chXDv X-Received: by 10.28.178.198 with SMTP id b189mr3328485wmf.8.1496925942764; Thu, 08 Jun 2017 05:45:42 -0700 (PDT) Received: from platinum (2a01cb0c03c651000226b0fffeed02fc.ipv6.abo.wanadoo.fr. [2a01:cb0c:3c6:5100:226:b0ff:feed:2fc]) by smtp.gmail.com with ESMTPSA id l93sm6295492wrc.46.2017.06.08.05.45.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Jun 2017 05:45:42 -0700 (PDT) Date: Thu, 8 Jun 2017 14:45:40 +0200 From: Olivier Matz To: Bruce Richardson Cc: "Ananyev, Konstantin" , "Verkamp, Daniel" , "dev@dpdk.org" Message-ID: <20170608144540.5a8e3603@platinum> In-Reply-To: <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> References: <20170602200337.50743-1-daniel.verkamp@intel.com> <20170602201213.51143-1-daniel.verkamp@intel.com> <2601191342CEEE43887BDE71AB9772583FB05190@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB05216@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jun 2017 12:45:43 -0000 On Tue, 6 Jun 2017 15:56:28 +0100, Bruce Richardson wrote: > On Tue, Jun 06, 2017 at 02:19:21PM +0100, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Richardson, Bruce > > > Sent: Tuesday, June 6, 2017 1:42 PM > > > To: Ananyev, Konstantin > > > Cc: Verkamp, Daniel ; dev@dpdk.org > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konstantin wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so members > > > > > > of struct rte_ring are 128 byte aligned, > > > > > > >and therefore the whole struct needs 128-byte alignment according to the ABI > > > > > > so that the 128-byte alignment of the fields can be guaranteed. > > > > > > > > > > > > Ah ok, missed the fact that rte_ring is 128B aligned these days. > > > > > > BTW, I probably missed the initial discussion, but what was the reason for that? > > > > > > Konstantin > > > > > > > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems unnecessary if the cache line is only 64 bytes. An > > > alternate > > > > > fix would be to just use cache line alignment for these fields (since memzones are already cache line aligned). > > > > > > > > Yes, had the same thought. > > > > > > > > > Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h? > > > > > > > > Might be, would be good to hear opinion the author of that change. > > > > > > It gives improved performance for core-2-core transfer. > > > > You mean empty cache-line(s) after prod/cons, correct? > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries? > > Something like that: > > struct rte_ring { > > ... > > struct rte_ring_headtail prod __rte_cache_aligned; > > EMPTY_CACHE_LINE __rte_cache_aligned; > > struct rte_ring_headtail cons __rte_cache_aligned; > > EMPTY_CACHE_LINE __rte_cache_aligned; > > }; > > > > Konstantin > > Sure. That should probably work too. > > /Bruce I also agree with Konstantin's proposal. One question though: since it changes the alignment constraint of the rte_ring structure, I think it is an ABI breakage: a structure including the rte_ring structure inherits from this constraint. How could we handle that, knowing this is probably a rare case?