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Fri, 9 Jun 2017 17:29:16 +0000 Date: Fri, 9 Jun 2017 22:58:55 +0530 From: Jerin Jacob To: Stephen Hemminger Cc: Yerden Zhumabekov , "Ananyev, Konstantin" , "Richardson, Bruce" , "Verkamp, Daniel" , "dev@dpdk.org" Message-ID: <20170609172854.GA2828@jerin> References: <20170602201213.51143-1-daniel.verkamp@intel.com> <2601191342CEEE43887BDE71AB9772583FB05190@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB05216@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <6908e71a-c849-83d3-e86d-745acf9f9491@sts.kz> <20170609101625.09075858@xeon-e3> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170609101625.09075858@xeon-e3> User-Agent: Mutt/1.8.3 (2017-05-23) X-Originating-IP: [171.76.124.136] X-ClientProxiedBy: MA1PR01CA0079.INDPRD01.PROD.OUTLOOK.COM (10.174.56.19) To BN3PR0701MB1718.namprd07.prod.outlook.com (10.163.39.17) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PR0701MB1718: X-MS-Office365-Filtering-Correlation-Id: be7767f4-ff57-4f09-7a3f-08d4af5d0f2c X-Microsoft-Antispam: UriScan:; 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> > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > struct rte_ring_headtail cons __rte_cache_aligned; > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > }; > > > > > > Konstantin > > > > > > > I'm curious, can anyone explain, how does it actually affect > > performance? Maybe we can utilize it application code? > > I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines. > If these cache lines change, then it will create false sharing. I see. I think, In such cases it is better to abstract as conditional compilation. The above logic has worst case cache memory requirement if CPU is 128B CL and no speculative prefetch.