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Mon, 12 Jun 2017 10:34:28 +0000 Date: Mon, 12 Jun 2017 16:04:11 +0530 From: Jerin Jacob To: "Ananyev, Konstantin" Cc: Stephen Hemminger , Yerden Zhumabekov , "Richardson, Bruce" , "Verkamp, Daniel" , "dev@dpdk.org" Message-ID: <20170612103409.GA4354@jerin> References: <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <6908e71a-c849-83d3-e86d-745acf9f9491@sts.kz> <20170609101625.09075858@xeon-e3> <20170609172854.GA2828@jerin> <2601191342CEEE43887BDE71AB9772583FB07AEC@IRSMSX109.ger.corp.intel.com> <20170612030730.GA6870@jerin> <2601191342CEEE43887BDE71AB9772583FB082EC@IRSMSX109.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2601191342CEEE43887BDE71AB9772583FB082EC@IRSMSX109.ger.corp.intel.com> User-Agent: Mutt/1.8.3 (2017-05-23) X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: BM1PR01CA0089.INDPRD01.PROD.OUTLOOK.COM (10.174.208.157) To BLUPR0701MB1714.namprd07.prod.outlook.com (10.163.85.140) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BLUPR0701MB1714: X-MS-Office365-Filtering-Correlation-Id: 87c2ebfc-c4e8-4a49-133c-08d4b17e9c2a X-Microsoft-Antispam: UriScan:; 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Yerden Zhumabekov ; Richardson, Bruce > > ; Verkamp, Daniel ; dev@dpdk.org > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > -----Original Message----- > > > Date: Sat, 10 Jun 2017 08:16:44 +0000 > > > From: "Ananyev, Konstantin" > > > To: Jerin Jacob , Stephen Hemminger > > > > > > CC: Yerden Zhumabekov , "Richardson, Bruce" > > > , "Verkamp, Daniel" > > > , "dev@dpdk.org" > > > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > > > > > -----Original Message----- > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > Sent: Friday, June 9, 2017 6:29 PM > > > > To: Stephen Hemminger > > > > Cc: Yerden Zhumabekov ; Ananyev, Konstantin ; Richardson, Bruce > > > > ; Verkamp, Daniel ; dev@dpdk.org > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > -----Original Message----- > > > > > Date: Fri, 9 Jun 2017 10:16:25 -0700 > > > > > From: Stephen Hemminger > > > > > To: Yerden Zhumabekov > > > > > Cc: "Ananyev, Konstantin" , "Richardson, > > > > > Bruce" , "Verkamp, Daniel" > > > > > , "dev@dpdk.org" > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > > On Fri, 9 Jun 2017 18:47:43 +0600 > > > > > Yerden Zhumabekov wrote: > > > > > > > > > > > On 06.06.2017 19:19, Ananyev, Konstantin wrote: > > > > > > > > > > > > > >>>> Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h? > > > > > > >>> Might be, would be good to hear opinion the author of that change. > > > > > > >> It gives improved performance for core-2-core transfer. > > > > > > > You mean empty cache-line(s) after prod/cons, correct? > > > > > > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries? > > > > > > > Something like that: > > > > > > > struct rte_ring { > > > > > > > ... > > > > > > > struct rte_ring_headtail prod __rte_cache_aligned; > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > struct rte_ring_headtail cons __rte_cache_aligned; > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > }; > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > > > I'm curious, can anyone explain, how does it actually affect > > > > > > performance? Maybe we can utilize it application code? > > > > > > > > > > I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines. > > > > > If these cache lines change, then it will create false sharing. > > > > > > > > I see. I think, In such cases it is better to abstract as conditional > > > > compilation. The above logic has worst case cache memory > > > > requirement if CPU is 128B CL and no speculative prefetch. > > I suppose we can keep exactly the same logic as we have now: > archs with 64B cache-line would have an empty cache line, > for archs with 128B cacheline - no. > Is that what you are looking for? Its valid to an arch with 128B cache-line and speculative cache prefetch. (Cavium's recent SoCs comes with this property) IMHO, Instead of making 128B as NOOP. We can introduce a new conditional compilation flag(CONFIG_RTE_ARCH_SPECULATIVE_PREFETCH or something like that) to decide the empty line and I think, In future we can use the same config for similar use cases. Jerin > Konstantin > > > > > > > I think this is already done for rte_ring.h: > > > http://dpdk.org/browse/dpdk/tree/lib/librte_ring/rte_ring.h#n119 > > > > Yes. The suggestion was in the context of when introducing the > > EMPTY_CACHE_LINE scheme, it should be a function of ARCH has > > speculative next cache-line prefetch or not? > > > > > > > > Konstantin > > > > > > > > >