From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 9DE1FDE3 for ; Mon, 12 Jun 2017 13:09:13 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 12 Jun 2017 04:09:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,333,1493708400"; d="scan'208";a="866997941" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.28]) by FMSMGA003.fm.intel.com with SMTP; 12 Jun 2017 04:09:08 -0700 Received: by (sSMTP sendmail emulation); Mon, 12 Jun 2017 12:09:08 +0100 Date: Mon, 12 Jun 2017 12:09:07 +0100 From: Bruce Richardson To: Jerin Jacob Cc: "Ananyev, Konstantin" , Stephen Hemminger , Yerden Zhumabekov , "Verkamp, Daniel" , "dev@dpdk.org" Message-ID: <20170612110907.GA64736@bricha3-MOBL3.ger.corp.intel.com> References: <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <6908e71a-c849-83d3-e86d-745acf9f9491@sts.kz> <20170609101625.09075858@xeon-e3> <20170609172854.GA2828@jerin> <2601191342CEEE43887BDE71AB9772583FB07AEC@IRSMSX109.ger.corp.intel.com> <20170612030730.GA6870@jerin> <2601191342CEEE43887BDE71AB9772583FB082EC@IRSMSX109.ger.corp.intel.com> <20170612103409.GA4354@jerin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170612103409.GA4354@jerin> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.8.1 (2017-04-11) Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Jun 2017 11:09:14 -0000 On Mon, Jun 12, 2017 at 04:04:11PM +0530, Jerin Jacob wrote: > -----Original Message----- > > Date: Mon, 12 Jun 2017 10:18:39 +0000 > > From: "Ananyev, Konstantin" > > To: Jerin Jacob > > CC: Stephen Hemminger , Yerden Zhumabekov > > , "Richardson, Bruce" , > > "Verkamp, Daniel" , "dev@dpdk.org" > > > > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Monday, June 12, 2017 4:08 AM > > > To: Ananyev, Konstantin > > > Cc: Stephen Hemminger ; Yerden Zhumabekov ; Richardson, Bruce > > > ; Verkamp, Daniel ; dev@dpdk.org > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > -----Original Message----- > > > > Date: Sat, 10 Jun 2017 08:16:44 +0000 > > > > From: "Ananyev, Konstantin" > > > > To: Jerin Jacob , Stephen Hemminger > > > > > > > > CC: Yerden Zhumabekov , "Richardson, Bruce" > > > > , "Verkamp, Daniel" > > > > , "dev@dpdk.org" > > > > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > > Sent: Friday, June 9, 2017 6:29 PM > > > > > To: Stephen Hemminger > > > > > Cc: Yerden Zhumabekov ; Ananyev, Konstantin ; Richardson, Bruce > > > > > ; Verkamp, Daniel ; dev@dpdk.org > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > > -----Original Message----- > > > > > > Date: Fri, 9 Jun 2017 10:16:25 -0700 > > > > > > From: Stephen Hemminger > > > > > > To: Yerden Zhumabekov > > > > > > Cc: "Ananyev, Konstantin" , "Richardson, > > > > > > Bruce" , "Verkamp, Daniel" > > > > > > , "dev@dpdk.org" > > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > > > > On Fri, 9 Jun 2017 18:47:43 +0600 > > > > > > Yerden Zhumabekov wrote: > > > > > > > > > > > > > On 06.06.2017 19:19, Ananyev, Konstantin wrote: > > > > > > > > > > > > > > > >>>> Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h? > > > > > > > >>> Might be, would be good to hear opinion the author of that change. > > > > > > > >> It gives improved performance for core-2-core transfer. > > > > > > > > You mean empty cache-line(s) after prod/cons, correct? > > > > > > > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries? > > > > > > > > Something like that: > > > > > > > > struct rte_ring { > > > > > > > > ... > > > > > > > > struct rte_ring_headtail prod __rte_cache_aligned; > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > struct rte_ring_headtail cons __rte_cache_aligned; > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > }; > > > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > > > > > > I'm curious, can anyone explain, how does it actually affect > > > > > > > performance? Maybe we can utilize it application code? > > > > > > > > > > > > I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines. > > > > > > If these cache lines change, then it will create false sharing. > > > > > > > > > > I see. I think, In such cases it is better to abstract as conditional > > > > > compilation. The above logic has worst case cache memory > > > > > requirement if CPU is 128B CL and no speculative prefetch. > > > > I suppose we can keep exactly the same logic as we have now: > > archs with 64B cache-line would have an empty cache line, > > for archs with 128B cacheline - no. > > Is that what you are looking for? > > Its valid to an arch with 128B cache-line and speculative cache prefetch. > (Cavium's recent SoCs comes with this property) > IMHO, Instead of making 128B as NOOP. We can introduce a new conditional > compilation flag(CONFIG_RTE_ARCH_SPECULATIVE_PREFETCH or something like > that) to decide the empty line and I think, In future we can use > the same config for similar use cases. > > Jerin > I'd rather not make it that complicated, and definitely don't like adding in more build time config options. Initially, I had the extra padding always-present, but it was felt that it made the resulting structure too big. For those systems with 128B cachelines, is the extra 256 bytes of space per ring really a problem given modern systems have ram in the 10's of Gigs? /Bruce