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VI1PR0501MB2046; 5:lM5l2eDd8RRWh0B3twOiGChDYffTCe1aicfH8nrcLdV5W7hyk92yhfQvg7mQxPrxCulJfbXxKDGR7CGE219VoXnhNFw6zU324O2wS81WRjzNRD5FIYpYcuiB/eIBLvy/AZx/Dbn65TQe6TFraatWqih6FA9Nvl0VX1qE9bR4u1tEDSsqYC/O/BavffIVr9XWE0WIUwrJNHST1pedmzhnMuRxcDxJN0653MDQ72/d+gnjPbRoKzHRSazpgvUGPmss8OYzuMp3aRE0/ZY5WuW5wHb/zJpbHc04oGxiScMnfwk5JYvi4hXbqinEGm43AuXmvPBJn0i1YMd6MPfFx4JFWDW42bo9voD5puIhSNXawX9xl6A8W3s5c+GHQplucxZJJ7EG7q6QKdSCXgpxlIPL0b5aoo3eIRpd9/AynAdS35yFmMCN0jy0bhVXrtOpcWXUocNJxDxTlpiTmt4V6FnC/NQgfDcuEP3A+A70Is2lJoerAIkb+WMyBG2zbIv7LCAG; 24:WKa33DTanLQKnVnknGPOimR0GU85H70yds6hls+m3K02yawvxPnXH8M8Q/R/WojPCNJ8CwuMJt6V1PUTjWJUcst40zeeAmUKuZJOK5stjwQ= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; VI1PR0501MB2046; 7:cBG6/MAHUQlzzo/iKOz60kOluTwzpScRNCR9grej3FJLO1DxvCOaTxb4cTnjrJJt+/yliJZFu7i5mwsZdEcuyKVKU6snECPs+bI8SK4fO/fMs9cE1ht3CJe3wkeFMn3z+4+VlItBd/wnTNYvqM/bwg/cvCmuNf8asIYqQBGwoti5LEItMLi9vw2f1++GovvSF/2q3WwSKKatsykbUKiKoDLyAyDP9XOvip2OEslavHKIL105kzxFBQPwAR07R9LD+AeqlZBdyEJZoze7h17/qbOva9Rqwrn2egaekYqlY9bCyofHIS8Ta1D7VUQw0i9yqk2k/11z13XFl0Zhh3MbvHQ0xSGtYHSxDDwAE7r39roXkPfRPMOxtSGe3UZHmA6r0n9M365r/owc0T0jNU2kGxSZYdTMxavvl4Ot+hXjN96aCSiK0lFhQDDG8e0WEY2AeFnZvfCXHaX4O5MN80gN0zw0FSD2AESPhrMg/HdYkpktoLuct5AM2FfPDgprafpyqDgD3gMXH7Vt9zvMDvIfUhD1TDqp0xSlDTDm5kdqsB94XMTK/L7nn/0ijGxGvv2pRkKzT5aHHn2RJVcbw2WBVMrXaUXyuZohV6Iax77nq0rLEGYaBwwkpd1o5XRteAx4VV9krFdSAGGmKa5sVde2hb5cFZtQMYg1ECb3FP1FMBpnXFJ8zzgBMDfzj/KLfKaW864mrDS87bxQAI309jFtY0gpOlvYS/kz7f2GmFHzby2t5arYq70LgmPibkz5PiuqzEy5dHK9doSAxui8z6pXCy+MqH2NY2lIc1bClVRPu7E= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2017 17:41:42.7611 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0501MB2046 Subject: Re: [dpdk-dev] [PATCH v2 5/5] net/mlx5: add vectorized Rx/Tx burst for SSE4.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Jul 2017 17:41:46 -0000 On Wed, Jul 05, 2017 at 10:21:26AM +0200, Nélio Laranjeiro wrote: > On Tue, Jul 04, 2017 at 05:38:44PM -0700, Yongseok Koh wrote: > > On Tue, Jul 04, 2017 at 10:58:52AM +0200, Nélio Laranjeiro wrote: > > > Yongseok, some comments in this huge and great work, > > > > > > On Fri, Jun 30, 2017 at 12:23:33PM -0700, Yongseok Koh wrote: > > > > To make vectorized burst routines enabled, it is required to run on x86_64 > > > > architecture which can support at least SSE4.1. If all the conditions are > > > > met, the vectorized burst functions are enabled automatically. The decision > > > > is made individually on RX and TX. There's no PMD option to make a > > > > selection. > > > > > > > > Signed-off-by: Yongseok Koh > > > > --- > > > > drivers/net/mlx5/Makefile | 10 + > > > > drivers/net/mlx5/mlx5_defs.h | 18 + > > > > drivers/net/mlx5/mlx5_ethdev.c | 28 +- > > > > drivers/net/mlx5/mlx5_rxq.c | 55 +- > > > > drivers/net/mlx5/mlx5_rxtx.c | 339 ++------ > > > > drivers/net/mlx5/mlx5_rxtx.h | 283 ++++++- > > > > drivers/net/mlx5/mlx5_rxtx_vec_sse.c | 1451 ++++++++++++++++++++++++++++++++++ > > > > drivers/net/mlx5/mlx5_txq.c | 2 +- > > > > 8 files changed, 1909 insertions(+), 277 deletions(-) > > > > create mode 100644 drivers/net/mlx5/mlx5_rxtx_vec_sse.c > > > > > > > > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > > > > index 51e258a15..2d0894fcd 100644 > > > > --- a/drivers/net/mlx5/mlx5_rxtx.h > > > > +++ b/drivers/net/mlx5/mlx5_rxtx.h > > [...] > > > > + txq_complete(txq); > > > > + /* A CQE slot must always be available. */ > > > > + assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); > > > > > > This assert should be moved to the txq_complete(), or it should not be > > > an assert. > > txq_complete() is a common function, so this can't force to spare at least one > > slot in a completion queue. This assert is to force to allocate enough CQE slots > > by accurate calculation as completion is suppressed by MLX5_TX_COMP_THRESH. If > > the CQ size is well defined (e.g. size of Tx ring / MLX5_TX_COMP_THRESH), it > > doesn't need to check deficiency of CQ slot but checking slots in Tx ring > > (max_elts) is sufficient. If you are okay with this, please let me know, then > > I'll send out v3. > > Just using your comment... > /* A CQE slot must always be available. */ > > This is always true in any Tx function where this assumption should be > true to avoid testing it before posting a completion request and thus > avoid cycles waste and this independently of the computation for the CQ > ring size. > > As it is an assert it is only present to help the developer in error > code he developed (or for a user to point an issue in the code), this > can be any-where in the Tx data path. It becomes useful for any Tx > function using this txq_complete(). > > If this assert is only related to your code, it may means it should be > an if which avoids to post a completion request when no slots are > available. I think I was wrong about the assert. If the Tx ring is full (max_elts == 0), then there won't be any empty slot left in CQ. I'll remove the two asserts. Thanks Yongseok