Re: [dpdk-dev] Question on mlx5 PMD txq memory registration

["Nélio Laranjeiro" <nelio.laranjeiro@6wind.com>]

On Wed, Jul 19, 2017 at 09:21:39AM +0300, Sagi Grimberg wrote:
> 
> > There is none, if you send a burst of 9 packets each one coming from a
> > different mempool the first one will be dropped.
> 
> Its worse than just a drop, without debug enabled the error completion
> is ignored, and the wqe_pi is taken from an invalid field, which leads
> to bogus mbufs free (elts_tail is not valid).

Right
 
> > > AFAICT, it is the driver responsibility to guarantee to never deregister
> > > a memory region that has inflight send operations posted, otherwise
> > > the send operation *will* complete with a local protection error. Is
> > > that taken care of?
> > 
> > Up to now we have assumed that the user knows its application needs and
> > he can increase this cache size to its needs through the configuration
> > item.
> > This way this limit and guarantee becomes true.
> 
> That is an undocumented assumption.

I agree it should be documented, in reality you are the first one we
know having this issue.
 
> > > Another question, why is the MR cache maintained per TX queue and not
> > > per device? If the application starts N TX queues then a single mempool
> > > will be registered N times instead of just once. Having lots of MR
> > > instances will pollute the device ICMC pretty badly. Am I missing
> > > something?
> > 
> > Having this cache per device needs a lock on the device structure while
> > threads are sending packets.
> 
> Not sure why it needs a lock at all. it *may* need an rcu protection
> or rw_lock if at all.

Tx queues may run on several CPU there is a need to be sure this array
cannot be modified by two threads at the same time.  Anyway it is
costly.

> > Having such locks cost cycles, that is why
> > the cache is per queue.  Another point is, having several mempool per
> > device is something common, whereas having several mempool per queues is
> > not, it seems logical to have this cache per queue for those two
> > reasons.
> > 
> > 
> > I am currently re-working this part of the code to improve it using
> > reference counters instead. The cache will remain for performance
> > purpose.  This will fix the issues you are pointing.
> 
> AFAICT, all this caching mechanism is just working around the fact
> that mlx5 allocates resources on top of the existing verbs interface.
> I think it should work like any other pmd driver, i.e. use mbuf the
> physical addresses.
> 
> The mlx5 device (like all other rdma devices) has a global DMA lkey that
> spans the entire physical address space. Just about all the kernel
> drivers heavily use this lkey. IMO, the mlx5_pmd driver should be able
> to query the kernel what this lkey is and ask for the kernel to create
> the QP with privilege level to post send/recv operations with that lkey.
> 
> And then, mlx5_pmd becomes like other drivers working with physical
> addresses instead of working around the memory registration sub-optimally.

It is one possibility discussed also with Mellanox guys, the point is
this breaks the security point of view which is also an important stuff.
If this is added in the future it will certainly be as an option, this
way both will be possible, the application could then choose about
security vs performance.

I don't know any planning on this from Mellanox side, maybe Shahaf have.

> And while were on the subject, what is the plan of detaching mlx5_pmd
> from its MLNX_OFED dependency? Mellanox has been doing a good job
> upstreaming the needed features (rdma-core). CC'ing Leon (who is
> co-maintaining the user-space rdma tree.

This is also a in progress in PMD part, it should be part of the next
DPDK release.

-- 
Nélio Laranjeiro
6WIND