From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f179.google.com (mail-wr0-f179.google.com [209.85.128.179]) by dpdk.org (Postfix) with ESMTP id 303017D3A for ; Wed, 23 Aug 2017 13:39:18 +0200 (CEST) Received: by mail-wr0-f179.google.com with SMTP id z91so4692478wrc.4 for ; Wed, 23 Aug 2017 04:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=CkcbfJjyP1A3aok25T+BQQb27+JrPQWzo+40uNQgzrQ=; b=ejG1t3yI2B7Ce9Zh70mCSkQeEBM147qTk2Aq5qk5342EdmSfjQRUC7Ixr2yOzC2m5U 5luRjCz5hMDQ4aPzOeMMmxfzrhMI3c4+wvtH25wvVWtozwHGnECTiu9HnhrSouHdOJ/E Q91MR9dAY43s29MJCHpzego/7kr8GcvI+jekLZhBxj/4piON493zfsO8fjQsheSK2rH/ qM2/Z47uB0mZBkMm9lhTZ1I5bj62AtGW7TvUHa/8ROWyRA31iXYcEFsdVDdpXMXWSWHF 0eArMdvIFcCXHPbeG+7gkUilkObJ8b0nbQe00tG1cl2uTipJKe3isJqAcxlsMz2HyfZC ny0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=CkcbfJjyP1A3aok25T+BQQb27+JrPQWzo+40uNQgzrQ=; b=OeCBTbRRlneYzucSQvjPdLGTdqX2bBepWSRRJ2oL9WSrOac+Pt/sc7EYJ3m24vmS6W mPUSBZoiGYXXTVoLHKo8vD98im4+wJ8s5x2r6eZP1pb8RuOxKtZKN8rOnc7i9o6Cy4Di wdIAibhd/EDzlcEota9GtIKe4E5BiSSKTM0QycS5A5LMaizirQcHgeazZXEXeLCIicLM VGd+n88L4+i70aYB5uxom1YrkrD+ouQ4NYTT9dRmnm0MSADtLyZLO/jQ9UIEMlhClwpO MfhQi2A9AZPObIPu9bAGqbg1Nx4Nip3nprrWnrZOHhgjxeLv2wlkeqxzMxvcK/ebWgYq JpTQ== X-Gm-Message-State: AHYfb5j8uUSKKOF5PmFc+HuwH3WcGcYN/Hn3moI7s27XPEOttiF3/CW9 PMDuD6YYZc98JVqpzbxWMQ== X-Received: by 10.223.164.88 with SMTP id e24mr1540884wra.64.1503488357805; Wed, 23 Aug 2017 04:39:17 -0700 (PDT) Received: from autoinstall.dev.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id b13sm1005687wrh.41.2017.08.23.04.39.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Aug 2017 04:39:17 -0700 (PDT) Date: Wed, 23 Aug 2017 13:39:08 +0200 From: =?iso-8859-1?Q?N=E9lio?= Laranjeiro To: Sagi Grimberg Cc: dev@dpdk.org, Adrien Mazarguil , Shahaf Shuler Message-ID: <20170823113908.GW12995@autoinstall.dev.6wind.com> References: <1503301622-14220-1-git-send-email-sagi@grimberg.me> <1503301622-14220-2-git-send-email-sagi@grimberg.me> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1503301622-14220-2-git-send-email-sagi@grimberg.me> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 11:39:18 -0000 On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > From: Shahaf Shuler > > The reason for the requirement of a barrier between the txq writes > and the doorbell record writes is to avoid a case where the device > reads the doorbell record's new value before the txq writes are flushed > to memory. > > The current use of rte_wmb is not necessary, and can be replaced by > rte_compiler_barrier as it acts as a write memory barrier. > More details on this type of barrier can be found on [1] > > Replacing the rte_wmb is also expected to improve the throughput. > > [1] https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html > > Signed-off-by: Shahaf Shuler > Signed-off-by: Yongseok Koh > Signed-off-by: Alexander Solganik > Signed-off-by: Sagi Grimberg > --- > drivers/net/mlx5/mlx5_rxtx.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > index 7de1d10863e5..59b9ff24fb82 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.h > +++ b/drivers/net/mlx5/mlx5_rxtx.h > @@ -602,7 +602,7 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe) > uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg); > volatile uint64_t *src = ((volatile uint64_t *)wqe); > > - rte_wmb(); > + rte_compiler_barrier(); > *txq->qp_db = htonl(txq->wqe_ci); > /* Ensure ordering between DB record and BF copy. */ > rte_wmb(); > -- > 2.7.4 Acked-by: Nelio Laranjeiro -- Nélio Laranjeiro 6WIND