From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id EFD1F7D4F for ; Wed, 23 Aug 2017 15:11:46 +0200 (CEST) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Aug 2017 06:11:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,417,1498546800"; d="scan'208";a="121878008" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.24]) by orsmga004.jf.intel.com with SMTP; 23 Aug 2017 06:11:43 -0700 Received: by (sSMTP sendmail emulation); Wed, 23 Aug 2017 14:11:42 +0100 Date: Wed, 23 Aug 2017 14:11:42 +0100 From: Bruce Richardson To: =?iso-8859-1?Q?N=E9lio?= Laranjeiro Cc: Sagi Grimberg , dev@dpdk.org, Adrien Mazarguil , Shahaf Shuler Message-ID: <20170823131142.GA13944@bricha3-MOBL3.ger.corp.intel.com> References: <1503301622-14220-1-git-send-email-sagi@grimberg.me> <1503301622-14220-2-git-send-email-sagi@grimberg.me> <20170823113908.GW12995@autoinstall.dev.6wind.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170823113908.GW12995@autoinstall.dev.6wind.com> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.8.3 (2017-05-23) Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Aug 2017 13:11:47 -0000 On Wed, Aug 23, 2017 at 01:39:08PM +0200, Nélio Laranjeiro wrote: > On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > > From: Shahaf Shuler > > > > The reason for the requirement of a barrier between the txq writes > > and the doorbell record writes is to avoid a case where the device > > reads the doorbell record's new value before the txq writes are flushed > > to memory. > > > > The current use of rte_wmb is not necessary, and can be replaced by > > rte_compiler_barrier as it acts as a write memory barrier. > > More details on this type of barrier can be found on [1] > > > > Replacing the rte_wmb is also expected to improve the throughput. > > > > [1] https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html > > > > Signed-off-by: Shahaf Shuler > > Signed-off-by: Yongseok Koh > > Signed-off-by: Alexander Solganik > > Signed-off-by: Sagi Grimberg > > --- > > drivers/net/mlx5/mlx5_rxtx.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > > index 7de1d10863e5..59b9ff24fb82 100644 > > --- a/drivers/net/mlx5/mlx5_rxtx.h > > +++ b/drivers/net/mlx5/mlx5_rxtx.h > > @@ -602,7 +602,7 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe) > > uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg); > > volatile uint64_t *src = ((volatile uint64_t *)wqe); > > > > - rte_wmb(); > > + rte_compiler_barrier(); > > *txq->qp_db = htonl(txq->wqe_ci); > > /* Ensure ordering between DB record and BF copy. */ > > rte_wmb(); > > -- > > 2.7.4 > > Acked-by: Nelio Laranjeiro > While a compiler barrier may do on platforms with strong ordering, I'm wondering if the rte_smp_wmb() macro may be needed here to give compiler barrier or actual memory barrier depending on platform? /Bruce