From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0064.outbound.protection.outlook.com [104.47.1.64]) by dpdk.org (Postfix) with ESMTP id 54F551B631 for ; Fri, 10 Nov 2017 04:14:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=SzbnaOsMEDkhwO4Wtjs1UPhooiQhjo1Gkuli1DjxT3s=; b=f1pufoXv1dpwIX8jzNmKilYWbQ/m+89my6Tn681vK9UryXPwvGrkAypU5Q9K5WVBnUh45tVvW1jlN/Q53ras0xPC2hRUCo56+/E1C+W2i8Mb0t18hkyejnMY96XngQG2Vvj9jJXrda9/cCZKUEx1l0K3y3GRQ0cny8wslWTjboE= Received: from arm.com (113.29.88.7) by AM5PR0801MB1345.eurprd08.prod.outlook.com (2603:10a6:203:1f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.197.13; Fri, 10 Nov 2017 03:14:09 +0000 Date: Fri, 10 Nov 2017 11:12:58 +0800 From: Jianbo Liu To: Jerin Jacob Cc: Jia He , dev@dpdk.org, olivier.matz@6wind.com, konstantin.ananyev@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, Jia He , jie2.liu@hxt-semitech.com, bing.zhao@hxt-semitech.com Message-ID: <20171110031257.GD27104@arm.com> References: <1510118764-29697-1-git-send-email-hejianet@gmail.com> <1510278669-8489-1-git-send-email-hejianet@gmail.com> <1510278669-8489-2-git-send-email-hejianet@gmail.com> <20171110024609.GA5295@jerin> MIME-Version: 1.0 Content-Type: text/plain; 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Something like below. > > > Fix for the rte_panic() in mbuf_autotest on qualcomm arm64 server(...SoC > name...) > > Root cause: > > In __rte_ring_move_cons_head() > > ... > > do { > > /* Restore n as it may change every loop */ > > n =3D max; > > > > *old_head =3D r->cons.head; //1st load > > const uint32_t prod_tail =3D r->prod.tail; //2nd load > > > > cpu1(producer) cpu2(consumer) cpu3(consumer) > > load r->prod.tail > > in enqueue: > > load r->cons.tail > > load r->prod.head > > > > store r->prod.tail > > > > load r->cons.head > > load r->prod.tail > > ... > > store r->cons.{head,tai= l} > > load r->cons.head > > > > In weak memory order architectures(powerpc,arm), the 2nd load might be > > reodered before the 1st load, that makes *entries is bigger than we > > wanted. This nasty reording messed enque/deque up. Then, r->cons.head > > will be bigger than prod_tail, then make *entries very big and the > > consumer will go forward incorrectly. > > > > After this patch, even with above context switches, the old cons.head > > will be recaculated after failure of rte_atomic32_cmpset. So no race > > conditions left. > > > > There is no such issue on X86, because X86 is strong memory order model= . > > But rte_smp_rmb() doesn't have impact on runtime performance on X86, so > > keep the same code without architectures specific concerns. > > > > Signed-off-by: Jia He > > Signed-off-by: jie2.liu@hxt-semitech.com > > Signed-off-by: bing.zhao@hxt-semitech.com > > =E2=9E=9C [master][dpdk.org] $ ./devtools/checkpatches.sh > > ### ring: guarantee load/load order in enqueue and dequeue > > WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a > separate line > #58: FILE: lib/librte_ring/rte_ring.h:414: > + * memory model. It is noop on x86 */ > > WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a > separate line > #70: FILE: lib/librte_ring/rte_ring.h:527: > + * memory model. It is noop on x86 */ > > total: 0 errors, 2 warnings, 22 lines checked > > 0/1 valid patch > =E2=9E=9C [master][dpdk.org] $ ./devtools/check-git-log.sh > Wrong tag: > Signed-off-by: jie2.liu@hxt-semitech.com > Signed-off-by: bing.zhao@hxt-semitech.com > > > With above fixes: > Acked-by: Jerin Jacob > > > Acked-by: Jianbo Liu And add it to stable. Cc: stable@dpdk.org -- IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.