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CY1PR07MB2523; 6:ZR7DQhRbyfdLK7YJ69UhX64wTz77sxLQJEMcSCD4ZoFOYR+FyU9Lk7nMaAwLIqV9Cpo9Hjb+nrw4KvXTmhsYRT7DVJjbB7XiR7ceev2stYBrPTN8Wbe4sAZ4S/bvSjbprQa/8U51QP9DPfG6/U2Zfwjk4JrwLGGp7t3fL8pprMaxZnSFrkn3BT+ZwcJribbZZRbscbAkgSsXBpZjFDvtqwEnQKx+GxNnKSbYNw7I4IFnqDW83Zc5jbUsQUqBP6N3T7tQgU8bjqDruZgEQVFZJ5RTlQVqKG2NnTA34EDX45PoimVIwizo8uJw7zl6eRFrHW4MbwF9b6/H6Z2quHAiayZ6L2Ifq7Uiy89rUmS+KrQ=; 5:zQyHnF2gKZo1VyCAIz4pJruEQc8fT2K+Jnhxj2Mkj97qG/zT8t3epmmcw7pUGwTsj8YcIsqbeXLgjwD9vPRVLNsjMbpmG5x0xdrzrQ5lAl6O70ITCFyP3YNu52eyJJButpEcyNNXIf2NwaLv/E3QWjVTLj+NaAfvYFEjrG3zbKI=; 24:PtdvDTDK0xMV6ZM3PqOj9gNBmaK0d0E0PQw4r+cJbm5huqSPelNtRw6nznh2z2owfI0a8fzLnwdo7uAdr6R/eGRfJpgFFIyL4vVPCfvVRZg=; 7:W6YsycdK22kxYdrcZSwry86Az6Z0lwhPgiOxE3UztkP6hC4C6Y/1dB4MoY0fIaRWgj6bNh8/ErPf4yv4kzNEUDHxlZZLkBtEAH2xZC5j03wBN+AClR0d+LYN9tB2PU3zaLKHaVPm3a6xWCcZ0HjTG3y1nVqgRdA97gCU2GJGfRDYVLJTonAV3FvgkQEggZLYmSnZDYxj/dSBf60DosEAqqR1KN26LoxcPAXHyHWRX50dULzAuU2pfzhAS+91Jd2i SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2017 12:32:14.4386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0024097d-a388-4119-efda-08d5372539d0 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR07MB2523 Subject: Re: [dpdk-dev] [PATCH] arch/arm: optimization for memcpy on AArch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Nov 2017 12:32:19 -0000 -----Original Message----- > Date: Mon, 27 Nov 2017 15:49:45 +0800 > From: Herbert Guan > To: jerin.jacob@caviumnetworks.com, jianbo.liu@arm.com, dev@dpdk.org > CC: Herbert Guan > Subject: [PATCH] arch/arm: optimization for memcpy on AArch64 > X-Mailer: git-send-email 1.8.3.1 > + > +/************************************** > + * Beginning of customization section > + **************************************/ > +#define ALIGNMENT_MASK 0x0F > +#ifndef RTE_ARCH_ARM64_MEMCPY_STRICT_ALIGN > +// Only src unalignment will be treaed as unaligned copy C++ style comments. It may generate check patch errors. > +#define IS_UNALIGNED_COPY(dst, src) ((uintptr_t)(dst) & ALIGNMENT_MASK) > +#else > +// Both dst and src unalignment will be treated as unaligned copy > +#define IS_UNALIGNED_COPY(dst, src) \ > + (((uintptr_t)(dst) | (uintptr_t)(src)) & ALIGNMENT_MASK) > +#endif > + > + > +// If copy size is larger than threshold, memcpy() will be used. > +// Run "memcpy_perf_autotest" to determine the proper threshold. > +#define ALIGNED_THRESHOLD ((size_t)(0xffffffff)) > +#define UNALIGNED_THRESHOLD ((size_t)(0xffffffff)) Do you see any case where this threshold is useful. > + > +static inline void *__attribute__ ((__always_inline__)) > +rte_memcpy(void *restrict dst, const void *restrict src, size_t n) > +{ > + if (n < 16) { > + rte_memcpy_lt16((uint8_t *)dst, (const uint8_t *)src, n); > + return dst; > + } > + if (n < 64) { > + rte_memcpy_ge16_lt64((uint8_t *)dst, (const uint8_t *)src, n); > + return dst; > + } Unfortunately we have 128B cache arm64 implementation too. Could you please take care that based on RTE_CACHE_LINE_SIZE > + __builtin_prefetch(src, 0, 0); > + __builtin_prefetch(dst, 1, 0); See above point and Please use DPDK equivalents. rte_prefetch*()