From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0062.outbound.protection.outlook.com [104.47.40.62]) by dpdk.org (Postfix) with ESMTP id F419825E5 for ; Fri, 1 Dec 2017 06:19:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=hm2CRhcoYMDPXkmswsNXIflOqsFAVl0l24d1dDtU4Po=; b=Uax5JCi5/bU/jGMk+jHw2RTm1e1H+6Zr0Z7NXD45TrZgvW/nHC3tPGulLyO3yfsRjaVVC2sZ8fcwr3WuTe2yuL1t04GBdRmT7VEKee3uxCnEq5mn7ze31Qpm7NEQ/61AX8sVWHDHv045oSi18WC45b3UmV4ohlptk5O4rxm5hqk= Received: from Pavan-LT (103.16.71.47) by CY4PR07MB3463.namprd07.prod.outlook.com (10.171.252.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.282.5; Fri, 1 Dec 2017 05:19:47 +0000 Date: Fri, 1 Dec 2017 10:49:35 +0530 From: Pavan Nikhilesh Bhagavatula To: "Eads, Gage" , "jerin.jacobkollanukkaran@cavium.com" , "Van Haaren, Harry" , bruce.richardson@intel.com, "hemant.agrawal@nxp.com" , "nipun.gupta@nxp.com" , "Rao, Nikhil" Cc: dev@dpdk.org Message-ID: <20171201051934.4cuia3w53b2zcjx2@Pavan-LT> References: <20171130072406.15605-1-pbhagavatula@caviumnetworks.com> <20171130072406.15605-3-pbhagavatula@caviumnetworks.com> <9184057F7FC11744A2107296B6B8EB1E2BB0182B@FMSMSX108.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; 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On Thu, Nov 30, 2017 at 05:15:14PM +0000, Eads, Gage wrote: > Hi Pavan, > > > -----Original Message----- > > From: Pavan Nikhilesh [mailto:pbhagavatula@caviumnetworks.com] > > Sent: Thursday, November 30, 2017 1:24 AM > > To: jerin.jacobkollanukkaran@cavium.com; Eads, Gage > > ; Van Haaren, Harry ; > > Richardson, Bruce ; hemant.agrawal@nxp.com; > > nipun.gupta@nxp.com; Rao, Nikhil > > Cc: dev@dpdk.org; Pavan Nikhilesh > > Subject: [dpdk-dev] [PATCH 3/4] app/eventdev: add perf pipeline test > > > > This is a performance test case that aims at testing the following: > > 1. Measure the end-to-end performance of an event dev with a ethernet dev. > > 2. Maintain packet ordering from Rx to Tx. > > > > The perf pipeline test configures the eventdev with Q queues and P ports, where > > Q is nb_ethdev * nb_stages and P is nb_workers. > > > > The user can choose the number of workers and number of stages through the -- > > wlcores and the --stlist application command line arguments respectively. > > The probed ethernet devices act as producer(s) for this application. > > > > The ethdevs are configured as event Rx adapters that enables them to injects > > events to eventdev based the first stage schedule type list requested by the user > > through --stlist the command line argument. > > > > Based on the number of stages to process(selected through --stlist), the > > application forwards the event to next upstream queue and when it reaches last > > stage in the pipeline if the event type is ATOMIC it is enqueued onto ethdev Tx > > queue else to maintain ordering the event type is set to ATOMIC and enqueued > > onto the last stage queue. > > On packet Tx, application increments the number events processed and print > > periodically in one second to get the number of events processed in one second. > > > > Note: The --prod_type_ethdev is mandatory for running the application. > > > > Example command to run perf pipeline test: > > sudo build/app/dpdk-test-eventdev -c 0xf -s 0x8 --vdev=event_sw0 -- \ -- > > test=perf_pipeline --wlcore=1 --prod_type_ethdev --stlist=ao > > > > Signed-off-by: Pavan Nikhilesh > > > > > +static int > > +perf_pipeline_eventdev_setup(struct evt_test *test, struct evt_options > > +*opt) { > > + int ret; > > + int nb_ports; > > + int nb_queues; > > + int nb_stages = opt->nb_stages; > > + uint8_t queue; > > + uint8_t port; > > + uint8_t atq = evt_has_all_types_queue(opt->dev_id); > > + struct test_perf *t = evt_test_priv(test); > > + > > + nb_ports = evt_nr_active_lcores(opt->wlcores); > > + nb_queues = rte_eth_dev_count() * (nb_stages); > > + nb_queues += atq ? 0 : rte_eth_dev_count(); > > + > > + const struct rte_event_dev_config config = { > > + .nb_event_queues = nb_queues, > > + .nb_event_ports = nb_ports, > > + .nb_events_limit = 4096, > > + .nb_event_queue_flows = opt->nb_flows, > > + .nb_event_port_dequeue_depth = 128, > > + .nb_event_port_enqueue_depth = 128, > > + }; > > + > > + ret = rte_event_dev_configure(opt->dev_id, &config); > > + if (ret) { > > + evt_err("failed to configure eventdev %d", opt->dev_id); > > + return ret; > > + } > > + > > + struct rte_event_queue_conf q_conf = { > > + .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, > > + .nb_atomic_flows = opt->nb_flows, > > + .nb_atomic_order_sequences = opt->nb_flows, > > + }; > > + /* queue configurations */ > > + for (queue = 0; queue < nb_queues; queue++) { > > + if (atq) { > > + q_conf.event_queue_cfg = > > RTE_EVENT_QUEUE_CFG_ALL_TYPES; > > + } else { > > + uint8_t slot; > > + > > + slot = queue % (nb_stages + 1); > > + q_conf.schedule_type = slot == nb_stages ? > > + RTE_SCHED_TYPE_ATOMIC : > > + opt->sched_type_list[slot]; > > + } > > + > > + ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); > > + if (ret) { > > + evt_err("failed to setup queue=%d", queue); > > + return ret; > > + } > > + } > > + > > + /* port configuration */ > > + const struct rte_event_port_conf p_conf = { > > + .dequeue_depth = opt->wkr_deq_dep, > > + .enqueue_depth = 64, > > + .new_event_threshold = 4096, > > + }; > > + > > For the hard-coded event device (new_event_threshold, port_dequeue_depth, enqueue_depth) and port configuration (enqueue_depth, new_event_threshold) values, it would be better to use the values from rte_event_dev_info_get() and rte_event_port_default_conf_get() instead. > > Thanks, > Gage