From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 1D69D23D for ; Mon, 18 Dec 2017 16:46:10 +0100 (CET) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2017 07:46:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,422,1508828400"; d="scan'208";a="159789239" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.106]) by orsmga004.jf.intel.com with SMTP; 18 Dec 2017 07:46:07 -0800 Received: by (sSMTP sendmail emulation); Mon, 18 Dec 2017 15:46:07 +0000 Date: Mon, 18 Dec 2017 15:46:06 +0000 From: Bruce Richardson To: Konstantin Ananyev Cc: dev@dpdk.org Message-ID: <20171218154606.GA13148@bricha3-MOBL3.ger.corp.intel.com> References: <1512126771-27503-2-git-send-email-konstantin.ananyev@intel.com> <1513611253-8785-3-git-send-email-konstantin.ananyev@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1513611253-8785-3-git-send-email-konstantin.ananyev@intel.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.9.1 (2017-09-22) Subject: Re: [dpdk-dev] [PATCH v2 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Dec 2017 15:46:11 -0000 On Mon, Dec 18, 2017 at 03:34:13PM +0000, Konstantin Ananyev wrote: > On x86 it is possible to use lock-prefixed instructions to get > the similar effect as mfence. > As pointed by Java guys, on most modern HW that gives a better > performance than using mfence: > https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > That patch adopts that technique for rte_smp_mb() implementation. > On BDW 2.2 mb_autotest on single lcore reports 2X cycle reduction, > i.e. from ~110 to ~55 cycles per operation. > > Signed-off-by: Konstantin Ananyev > --- Acked-by: Bruce Richardson