From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02hn0233.outbound.protection.outlook.com [104.47.37.233]) by dpdk.org (Postfix) with ESMTP id 2470A1B023 for ; Mon, 18 Dec 2017 22:45:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=p26M0OQB3Tq9tLk4OCVKHdfp8HVP5wtobf89YyWLBvM=; b=XPRVCdmmZbYTFN4ARg+tweK3dbogIdggyAxuCalz6UxRoASniWujZT55KL82Q4l+iJhEhZ3i6yWgLc/0u5g0akgdShz3myT+wHMwHt4fek6AucUQLZ3tBiQLuW6cefYanKiRrDeCTpW1RSCxLjq7voxXW6qoOwZnDbS4i6t5t5Y= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Pavan.Bhagavatula@cavium.com; Received: from localhost.localdomain (111.93.218.67) by DM5PR07MB3467.namprd07.prod.outlook.com (10.164.153.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.323.15; Mon, 18 Dec 2017 21:45:16 +0000 From: Pavan Nikhilesh To: jerin.jacob@caviumnetworks.com, santosh.shukla@caviumnetworks.com, bruce.richardson@intel.com, harry.van.haaren@intel.com, gage.eads@intel.com, hemant.agrawal@nxp.com, nipun.gupta@nxp.com, liang.j.ma@intel.com Cc: dev@dpdk.org, Pavan Nikhilesh Date: Tue, 19 Dec 2017 03:14:01 +0530 Message-Id: <20171218214405.26763-8-pbhagavatula@caviumnetworks.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171218214405.26763-1-pbhagavatula@caviumnetworks.com> References: <20171130072406.15605-1-pbhagavatula@caviumnetworks.com> <20171218214405.26763-1-pbhagavatula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: HK2PR02CA0163.apcprd02.prod.outlook.com (10.171.30.23) To DM5PR07MB3467.namprd07.prod.outlook.com (10.164.153.22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fdee696c-2357-430b-040e-08d54660a23d X-Microsoft-Antispam: UriScan:; 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Measure the end-to-end performance of an event dev with a ethernet dev. 2. Maintain packet ordering from Rx to Tx. The pipeline queue test configures the eventdev with Q queues and P ports, where Q is (nb_ethdev * nb_stages) + nb_ethdev and P is nb_workers. The user can choose the number of workers and number of stages through the --wlcores and the --stlist application command line arguments respectively. The probed ethernet devices act as producer(s) for this application. The ethdevs are configured as event Rx adapters that enables them to injects events to eventdev based the first stage schedule type list requested by the user through --stlist the command line argument. Based on the number of stages to process(selected through --stlist), the application forwards the event to next upstream queue and when it reaches last stage in the pipeline if the event type is ATOMIC it is enqueued onto ethdev Tx queue else to maintain ordering the event type is set to ATOMIC and enqueued onto the last stage queue. On packet Tx, application increments the number events processed and print periodically in one second to get the number of events processed in one second. Note: The --prod_type_ethdev is mandatory for running the application. Example command to run pipeline queue test: sudo build/app/dpdk-test-eventdev -c 0xf -s 0x8 --vdev=event_sw0 -- \ --test=pipeline_queue --wlcore=1 --prod_type_ethdev --stlist=ao Signed-off-by: Pavan Nikhilesh --- app/test-eventdev/Makefile | 1 + app/test-eventdev/test_pipeline_queue.c | 193 ++++++++++++++++++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 app/test-eventdev/test_pipeline_queue.c diff --git a/app/test-eventdev/Makefile b/app/test-eventdev/Makefile index f2fb665d8..30bebfb2f 100644 --- a/app/test-eventdev/Makefile +++ b/app/test-eventdev/Makefile @@ -52,5 +52,6 @@ SRCS-y += test_perf_queue.c SRCS-y += test_perf_atq.c SRCS-y += test_pipeline_common.c +SRCS-y += test_pipeline_queue.c include $(RTE_SDK)/mk/rte.app.mk diff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test-eventdev/test_pipeline_queue.c new file mode 100644 index 000000000..851027cb7 --- /dev/null +++ b/app/test-eventdev/test_pipeline_queue.c @@ -0,0 +1,193 @@ +/* + * BSD LICENSE + * + * Copyright (C) Cavium, Inc 2017. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "test_pipeline_common.h" + +/* See http://dpdk.org/doc/guides/tools/testeventdev.html for test details */ + +static __rte_always_inline int +pipeline_queue_nb_event_queues(struct evt_options *opt) +{ + uint16_t eth_count = rte_eth_dev_count(); + + return (eth_count * opt->nb_stages) + eth_count; +} + +static int +worker_wrapper(void *arg) +{ + RTE_SET_USED(arg); + rte_panic("invalid worker\n"); +} + +static int +pipeline_queue_launch_lcores(struct evt_test *test, struct evt_options *opt) +{ + return pipeline_launch_lcores(test, opt, worker_wrapper); +} + +static int +pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt) +{ + int ret; + int nb_ports; + int nb_queues; + int nb_stages = opt->nb_stages; + uint8_t queue; + struct rte_event_dev_info info; + + nb_ports = evt_nr_active_lcores(opt->wlcores); + nb_queues = rte_eth_dev_count() * (nb_stages); + nb_queues += rte_eth_dev_count(); + + rte_event_dev_info_get(opt->dev_id, &info); + + const struct rte_event_dev_config config = { + .nb_event_queues = nb_queues, + .nb_event_ports = nb_ports, + .nb_events_limit = info.max_num_events, + .nb_event_queue_flows = opt->nb_flows, + .nb_event_port_dequeue_depth = + info.max_event_port_dequeue_depth, + .nb_event_port_enqueue_depth = + info.max_event_port_enqueue_depth, + }; + ret = rte_event_dev_configure(opt->dev_id, &config); + if (ret) { + evt_err("failed to configure eventdev %d", opt->dev_id); + return ret; + } + + struct rte_event_queue_conf q_conf = { + .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, + .nb_atomic_flows = opt->nb_flows, + .nb_atomic_order_sequences = opt->nb_flows, + }; + /* queue configurations */ + for (queue = 0; queue < nb_queues; queue++) { + uint8_t slot; + + slot = queue % (nb_stages + 1); + q_conf.schedule_type = slot == nb_stages ? + RTE_SCHED_TYPE_ATOMIC : + opt->sched_type_list[slot]; + + ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); + if (ret) { + evt_err("failed to setup queue=%d", queue); + return ret; + } + } + + /* port configuration */ + const struct rte_event_port_conf p_conf = { + .dequeue_depth = opt->wkr_deq_dep, + .enqueue_depth = info.max_event_port_dequeue_depth, + .new_event_threshold = info.max_num_events, + }; + + ret = pipeline_event_port_setup(test, opt, nb_queues, p_conf); + if (ret) + return ret; + + ret = pipeline_event_rx_adapter_setup(opt, nb_stages + 1, + p_conf); + if (ret) + return ret; + + if (!evt_has_distributed_sched(opt->dev_id)) { + uint32_t service_id; + rte_event_dev_service_id_get(opt->dev_id, &service_id); + ret = evt_service_setup(service_id); + if (ret) { + evt_err("No service lcore found to run event dev."); + return ret; + } + } + + ret = rte_event_dev_start(opt->dev_id); + if (ret) { + evt_err("failed to start eventdev %d", opt->dev_id); + return ret; + } + + return 0; +} + +static void +pipeline_queue_opt_dump(struct evt_options *opt) +{ + pipeline_opt_dump(opt, pipeline_queue_nb_event_queues(opt)); +} + +static int +pipeline_queue_opt_check(struct evt_options *opt) +{ + return pipeline_opt_check(opt, pipeline_queue_nb_event_queues(opt)); +} + +static bool +pipeline_queue_capability_check(struct evt_options *opt) +{ + struct rte_event_dev_info dev_info; + + rte_event_dev_info_get(opt->dev_id, &dev_info); + if (dev_info.max_event_queues < pipeline_queue_nb_event_queues(opt) || + dev_info.max_event_ports < + evt_nr_active_lcores(opt->wlcores)) { + evt_err("not enough eventdev queues=%d/%d or ports=%d/%d", + pipeline_queue_nb_event_queues(opt), + dev_info.max_event_queues, + evt_nr_active_lcores(opt->wlcores), + dev_info.max_event_ports); + } + + return true; +} + +static const struct evt_test_ops pipeline_queue = { + .cap_check = pipeline_queue_capability_check, + .opt_check = pipeline_queue_opt_check, + .opt_dump = pipeline_queue_opt_dump, + .test_setup = pipeline_test_setup, + .mempool_setup = pipeline_mempool_setup, + .ethdev_setup = pipeline_ethdev_setup, + .eventdev_setup = pipeline_queue_eventdev_setup, + .launch_lcores = pipeline_queue_launch_lcores, + .eventdev_destroy = pipeline_eventdev_destroy, + .mempool_destroy = pipeline_mempool_destroy, + .ethdev_destroy = pipeline_ethdev_destroy, + .test_result = pipeline_test_result, + .test_destroy = pipeline_test_destroy, +}; + +EVT_TEST_REGISTER(pipeline_queue); -- 2.14.1