From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by dpdk.org (Postfix) with ESMTP id 761781B024 for ; Sat, 6 Jan 2018 02:07:00 +0100 (CET) Received: by mail-pf0-f196.google.com with SMTP id m26so2861382pfj.11 for ; Fri, 05 Jan 2018 17:07:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=156CjoMIrgnOe5KZcoAOVIwmYIt8TGHngHBrQOvqafY=; b=YrkHlkq9nC0t459Z/2YP21so8HjoipF3OuXQtDLM7oCXNDaYCL1RKggA4CNEpSZNNa 4IKJFzR0TqpM3WOH2EhPMSCl8cpukaeN3CGWwxi6ifM1GTIOMYBSf5isTlEq7xst/V2c YyQvqkr6NeiCynzGYrej9mNtFqJWKas5nh+mZeRshl/sCuDmC9rhE8vdlEyjnL+MvK31 EJfvGI45C0RvD9moqEbc6nmzaSmoAi46+3SEbxnPV94qtggFsmuMZvYWxQOur3LpsKtd XsfLLFnoIp/UyXqtPfo0/9fBqbUgn1FvKeo4drDk5kV1SGIfUnpc708nliaiEj8z8YpL yXiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=156CjoMIrgnOe5KZcoAOVIwmYIt8TGHngHBrQOvqafY=; b=g+HnFNUlZ9sekuFAsVnR2winUvfy+GSdVLQhkFXWWExWdA93MYQ4KyYL5bkcrEbnrn kVwNj7ptnz0fTUG/o/XKv4ijs37ftgVRSnW4/9Kn5zX6oZs58GpoQyd5sqTiQy5HnV1N rKzIloC2cfjlteaap1EUoqOSSbSw/4nlMFUo61i+4rUG6gIbIKWRklTME9m8/ndTdKqn nkmZU8sred9U+04ZklOpkv11ZUMcWj74eIr/7J89dXfoU6NOjdxOEX2ks5/HU/20Tv8N Tqqt0q2whsdjo9TCQjFaMGIJdqvFcYtX9MAmWs2EZfFT8Nn3H1GiCqotwzaunGMe2ukO /VMw== X-Gm-Message-State: AKGB3mKljtvu4/oXCVm6xf12OvIFfUZiSR5Ojos5/g/P8QPUUhQV3BMx Jx/x+jiBUMzO2FOjPjgTT+cU1gfb41c= X-Google-Smtp-Source: ACJfBosHw6Y+4NbEm/Wn8PoRrwHvOs2aVp3kCscsc9JVj3kT9DQQ92psF4cwZAL1pD4JHtmds675HA== X-Received: by 10.99.151.26 with SMTP id n26mr3802575pge.87.1515200819040; Fri, 05 Jan 2018 17:06:59 -0800 (PST) Received: from xeon-e3.lan (204-195-18-133.wavecable.com. [204.195.18.133]) by smtp.gmail.com with ESMTPSA id p14sm12385018pgn.37.2018.01.05.17.06.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jan 2018 17:06:58 -0800 (PST) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger Date: Fri, 5 Jan 2018 17:06:42 -0800 Message-Id: <20180106010656.9167-2-stephen@networkplumber.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180106010656.9167-1-stephen@networkplumber.org> References: <20180106010656.9167-1-stephen@networkplumber.org> Subject: [dpdk-dev] [PATCH v2 01/15] eal: introduce atomic exchange operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Jan 2018 01:07:00 -0000 To handle atomic update of link status (64 bit), every driver was doing its own version using cmpset. Atomic exchange is a useful primitive in its own right; therefore make it a EAL routine. Signed-off-by: Stephen Hemminger --- .../common/include/arch/x86/rte_atomic.h | 24 +++++++ .../common/include/arch/x86/rte_atomic_32.h | 12 ++++ .../common/include/arch/x86/rte_atomic_64.h | 12 ++++ lib/librte_eal/common/include/generic/rte_atomic.h | 78 ++++++++++++++++++++++ 4 files changed, 126 insertions(+) diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h index 8469f97e193a..20d10cc18e4e 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h @@ -59,6 +59,18 @@ rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src) return res; } +static inline uint16_t +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val) +{ + asm volatile( + MPLOCKED + "xchgw %0, %1;" + : "=r" (val), "=m" (*dst) + : "0" (val), "m" (*dst) + : "memory"); /* no-clobber list */ + return val; +} + static inline int rte_atomic16_test_and_set(rte_atomic16_t *v) { return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1); @@ -133,6 +145,18 @@ rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) return res; } +static inline uint32_t +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val) +{ + asm volatile( + MPLOCKED + "xchgl %0, %1;" + : "=r" (val), "=m" (*dst) + : "0" (val), "m" (*dst) + : "memory"); /* no-clobber list */ + return val; +} + static inline int rte_atomic32_test_and_set(rte_atomic32_t *v) { return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1); diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_32.h b/lib/librte_eal/common/include/arch/x86/rte_atomic_32.h index fb3abf187998..43fa59355ac5 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_32.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_32.h @@ -98,6 +98,18 @@ rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) return res; } +static inline uint64_t +rte_atomic64_exchange(volatile uint64_t *dest, uint64_t val) +{ + uint64_t old; + + do { + old = *dest; + } while (rte_atomic64_t_cmpset(dest, old, val)); + + return old; +} + static inline void rte_atomic64_init(rte_atomic64_t *v) { diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h index 1a53a766bd72..fd2ec9c53796 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h @@ -71,6 +71,18 @@ rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) return res; } +static inline uint64_t +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val) +{ + asm volatile( + MPLOCKED + "xchgq %0, %1;" + : "=r" (val), "=m" (*dst) + : "0" (val), "m" (*dst) + : "memory"); /* no-clobber list */ + return val; +} + static inline void rte_atomic64_init(rte_atomic64_t *v) { diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h index 16af5ca57e01..97854df3d134 100644 --- a/lib/librte_eal/common/include/generic/rte_atomic.h +++ b/lib/librte_eal/common/include/generic/rte_atomic.h @@ -139,6 +139,32 @@ rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src) } #endif +/** + * Atomic exchange. + * + * (atomic) equivalent to: + * ret = *dst + * *dst = val; + * return ret; + * + * @param dst + * The destination location into which the value will be written. + * @param val + * The new value. + * @return + * The original value at that location + */ +static inline uint16_t +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val); + +#ifdef RTE_FORCE_INTRINSICS +static inline uint16_t +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val) +{ + return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST); +} +#endif + /** * The atomic counter structure. */ @@ -392,6 +418,32 @@ rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) } #endif +/** + * Atomic exchange. + * + * (atomic) equivalent to: + * ret = *dst + * *dst = val; + * return ret; + * + * @param dst + * The destination location into which the value will be written. + * @param val + * The new value. + * @return + * The original value at that location + */ +static inline uint32_t +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val); + +#ifdef RTE_FORCE_INTRINSICS +static inline uint32_t +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val) +{ + return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST); +} +#endif + /** * The atomic counter structure. */ @@ -644,6 +696,32 @@ rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) } #endif +/** + * Atomic exchange. + * + * (atomic) equivalent to: + * ret = *dst + * *dst = val; + * return ret; + * + * @param dst + * The destination location into which the value will be written. + * @param val + * The new value. + * @return + * The original value at that location + */ +static inline uint64_t +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val); + +#ifdef RTE_FORCE_INTRINSICS +static inline uint64_t +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val) +{ + return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST); +} +#endif + /** * The atomic counter structure. */ -- 2.15.1