From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id C81D91B010 for ; Mon, 8 Jan 2018 04:07:59 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jan 2018 19:07:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,329,1511856000"; d="scan'208";a="193139679" Received: from wuyanglong.sh.intel.com ([10.67.111.98]) by fmsmga006.fm.intel.com with ESMTP; 07 Jan 2018 19:07:57 -0800 From: Yanglong Wu To: dev@dpdk.org Cc: konstantin.ananyev@intel.com, Yanglong Wu Date: Mon, 8 Jan 2018 11:06:01 +0800 Message-Id: <20180108030601.5622-1-yanglong.wu@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120024026.152048-1-yanglong.wu@intel.com> References: <20171120024026.152048-1-yanglong.wu@intel.com> Subject: [dpdk-dev] [PATCH v5] net/ixgbe: fix l3fwd start failed on X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Jan 2018 03:08:00 -0000 L3fwd start failed on PF, for tx_q check failed. That occurred when the SRIOV is active and tx_q > rx_q. The tx_q is equal to nb_q_per_pool. The number of nb_q_per_pool should equeal to max number of queues supported by HW not nb_rx_q. Fixes: 27b609cbd1c6 (ethdev: move the multi-queue mode check to specific drivers) Signed-off-by: Yanglong Wu --- v5: Rework according to comments --- drivers/net/ixgbe/ixgbe_ethdev.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index ff19a564a..baaeee5d9 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -95,6 +95,9 @@ /* Timer value included in XOFF frames. */ #define IXGBE_FC_PAUSE 0x680 +/*Default value of Max Rx Queue*/ +#define IXGBE_MAX_RX_QUEUE_NUM 128 + #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ @@ -2194,9 +2197,10 @@ ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) return -EINVAL; } - RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q; - RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q; - + RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = + IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; + RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = + pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; return 0; } -- 2.11.0