From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by dpdk.org (Postfix) with ESMTP id 072E61B1B2 for ; Mon, 8 Jan 2018 16:34:16 +0100 (CET) Received: by mail-pg0-f65.google.com with SMTP id q12so5743327pgt.7 for ; Mon, 08 Jan 2018 07:34:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nVzTeVEDjnRwuubvRRYoqydTVLFdSxEKHzELW3n50h0=; b=dI17R0sf6HbYFyl/IwJ8qkFVKj19j0yAqCj4N+k93ieh9lI15wgz3kFzBx+p1O9Q0o uG1K4m4BvV6FsC1NgBdY8yaJBnQoTkVI11JX10gEbfLXhcGM5VBYlpbQbbVgldMPRn5m wEa/SQAN+2F8Ua6XtlWMUHjVAMNvTr4Ok3s1c/C59JhyF4/plFM4i7nNpe+tErUol9pQ z/POqWw9dvrX+9tac5iKoSt7DVY2zkRL0x/2zqWze/oH/LDJXriXl/Kbtg9E/wlVNAE9 4PoLQYeRRg9mvGVMtZ8mw3T5IlRukyYo1YI8ESQFNaqnEvINSWCkP+qGqD9+IgPwr9lC 3xFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nVzTeVEDjnRwuubvRRYoqydTVLFdSxEKHzELW3n50h0=; b=XUunfsQVPJTK9af7di8RV4esGP118Y01JA0QiO1hl0Ktalra03QreJu4I+58rBy2u5 jHfunw2aoIOFTjxiyC3L5B7wPD+nOoS3jBiuDBpl5PMyNhavw2V27SU1UUaQCCd/vpa+ ZuCL1IOBaB4dEbiEbINfO/wZAiaj8PDMIBgdM6fti0TPn2vxSc8zNWX7OwKUZ91APVpH 53iMHAOkHWtIpKzUq5MTkSlblQxZX0bgF4ZEiU1tssPjO1dyJMdmA0L+E/iduguKUTXa hgi/Ug1u1bsI0jg0zMwLtXbqPHZOPPi4d7S+4HUGQ6iAKOJbIG3/Hea9G10qgb3Rd08Y sGDA== X-Gm-Message-State: AKGB3mLMaaaO6cfOnBAOcxTvObi/K9NBtQpejrah0gSu7JzTKJAdQD9e /NI9sxcOKcUmOW7F5PEFsrFwgA== X-Google-Smtp-Source: ACJfBouhEzS/ghefwb2bExzDHut6YUbv2GZmlJPKRrTzON4TUod1J23mfZoeUCe2sxP0cZGjHHrNLQ== X-Received: by 10.101.74.69 with SMTP id a5mr9457022pgu.297.1515425656158; Mon, 08 Jan 2018 07:34:16 -0800 (PST) Received: from xeon-e3 (204-195-18-133.wavecable.com. [204.195.18.133]) by smtp.gmail.com with ESMTPSA id k62sm23508672pga.42.2018.01.08.07.34.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Jan 2018 07:34:16 -0800 (PST) Date: Mon, 8 Jan 2018 07:34:11 -0800 From: Stephen Hemminger To: Maxime Coquelin Cc: dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, santosh.shukla@caviumnetworks.com, anatoly.burakov@intel.com, thomas@monjalon.net, peterx@redhat.com Message-ID: <20180108073411.67f12201@xeon-e3> In-Reply-To: <20180108135127.25869-1-maxime.coquelin@redhat.com> References: <20180108135127.25869-1-maxime.coquelin@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] bus/pci: forbid VA as IOVA mode if IOMMU address width too small X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Jan 2018 15:34:17 -0000 On Mon, 8 Jan 2018 14:51:27 +0100 Maxime Coquelin wrote: > Intel VT-d supports different address widths for the IOVAs, from > 39 bits to 56 bits. > > While recent processors support at least 48 bits, VT-d emulation > currently only supports 39 bits. It makes DMA mapping to fail in this > case when using VA as IOVA mode, as user-space virtual addresses uses > up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt). > > This patch parses VT-d CAP register value available in sysfs, and > forbid VA as IOVA mode if the GAW is 39 bits or unknown. > > Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs") > > Cc: stable@dpdk.org > Signed-off-by: Maxime Coquelin > --- > Hi, > > I'm not super happy with the patch as it does platform specific things in > generic code, but there are no placeholder for IOMMU/VT-d at the moment. > > As this patch is to be backported to v17.11 LTS, it cannot be a big rework. > > If you have some suggestion to improve it, please let me know. > > The fix is quite urgent, as guest device assignment with vIOMMU is broken in > mainline & v17.11 LTS. > > Advantage of this fix over forbidding VA as IOVA when running in emulation is > that VT-d emulation will soon support 48 bits, so this is future proof. Also, > VT-d spec supports 39 bits, so we could have physical CPUs supporting it, even > if I don't know any. > > Thanks, > Maxime You are assumming that if IOMMU is present that it is being used (ie VFIO). What about the case of direct access to PF device via IGB_UIO? > +static inline bool > +pci_one_device_iommu_support_va(struct rte_pci_device *dev) > +{ This is not in fast path, there is no reason it should be inline