From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by dpdk.org (Postfix) with ESMTP id BDAF11B1C5 for ; Mon, 8 Jan 2018 16:38:51 +0100 (CET) Received: by mail-pf0-f193.google.com with SMTP id e76so1401440pfk.1 for ; Mon, 08 Jan 2018 07:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mC82TE5FuUB3+54KJAVoVMBMVfIKxLZoUVAv4is0vYo=; b=VgCy3JPLzq/i1MevgFPzZhznEi3EUGe6jWX8uJszVOO3j1b3SMOg3W3JNitOk97SOh DyIQGuTLU9mVjkU86Bjs2vyodwQKAYzLANwccVYbAXCefTwXCaSArFLWHZ/WsnZwIsoG tLGf8RMCRd0gyAJ0Wu6PvOUJYaSZe3ldwoiPMEx2kTLLeqVr75Md4Rni2d4c1QxbJiKO /DJBxaBjL4MZIEUef3DVtbt36M9+LZISCk37k/hhoEUkOnHTgGwHRRmrPSS/L78Eyf3M PZs5zU3ycKnOF9Oyvz4L0u2jjVRI4bMfAqeYyHk1i8jI2cRKonJ00MQdDX8v2udYTBGx X1iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mC82TE5FuUB3+54KJAVoVMBMVfIKxLZoUVAv4is0vYo=; b=kC/gvTeCtIV1iKloqvK6yk64pCnCC6h3sNCL3DlHXBVxIG7YPy6BRBkgAxLkIQ3+tt FufqBJh/TNSGBUUuFy3vB+qKdF0etG2cxAd4TEYHQkZCcNgY4rpPkcR3n9nwDNExxh2O 0ew4qhvKZohG11kFfA5kRWY2+nGRt+0evRuH+NTHgIslmR6Yjl1796JuF4Nt7kkjq4p7 cLA+Hs9JdP28lhfbKFl4LQc/8GcwUQEMTPyYZub3vezNCfeJpjaV9u/9vWwmG4cIBDVn mTYEqiKhpzrwJYs5/DgS9AoS4Ejqcs1jIP+2OUOHmWqfuMl31EHfyXmrxjMQTjgP63cV xIMg== X-Gm-Message-State: AKGB3mL4jkknbB9NkpiLpSeTF2ddZmrl5RtW61Ml3IEvNSq4SnSwU6uZ 1iZDflby8NImrB9MeSaR17p41A== X-Google-Smtp-Source: ACJfBoup6g/S7FTAgxqa9s8FtpQWIl0btrmi9A8Xxhya8Bkl6sVuhDH/s+QEA/nJ9iSJdqTQjEcSvA== X-Received: by 10.99.104.194 with SMTP id d185mr5878508pgc.404.1515425930892; Mon, 08 Jan 2018 07:38:50 -0800 (PST) Received: from xeon-e3 (204-195-18-133.wavecable.com. [204.195.18.133]) by smtp.gmail.com with ESMTPSA id h81sm30867242pfh.119.2018.01.08.07.38.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Jan 2018 07:38:50 -0800 (PST) Date: Mon, 8 Jan 2018 07:38:41 -0800 From: Stephen Hemminger To: Maxime Coquelin Cc: dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, santosh.shukla@caviumnetworks.com, anatoly.burakov@intel.com, thomas@monjalon.net, peterx@redhat.com Message-ID: <20180108073841.43c15072@xeon-e3> In-Reply-To: <20180108135127.25869-1-maxime.coquelin@redhat.com> References: <20180108135127.25869-1-maxime.coquelin@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] bus/pci: forbid VA as IOVA mode if IOMMU address width too small X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Jan 2018 15:38:52 -0000 On Mon, 8 Jan 2018 14:51:27 +0100 Maxime Coquelin wrote: > +static inline bool > +pci_one_device_iommu_support_va(struct rte_pci_device *dev) > +{ > +#if defined(RTE_ARCH_PPC_64) > + return false; > +#elif defined(RTE_ARCH_X86) > + The cleaner way to handle this kind of ifdef is: #ifdef RTE_ARCH_X86 static bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { .... } #elif defined(RTE_ARCH_PPC_64) static inline bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { return false; } #endif What about AMD64? Do all ARM processors have IOMMU, I think not.