From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id D55E21B00B for ; Tue, 9 Jan 2018 16:00:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from xuemingl@mellanox.com) with ESMTPS (AES256-SHA encrypted); 9 Jan 2018 17:00:08 +0200 Received: from dev-r630-06.mtbc.labs.mlnx (dev-r630-06.mtbc.labs.mlnx [10.12.205.180]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w09F07Pd017506; Tue, 9 Jan 2018 17:00:08 +0200 Received: from dev-r630-06.mtbc.labs.mlnx (localhost [127.0.0.1]) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7) with ESMTP id w09EBfdu146308; Tue, 9 Jan 2018 22:11:41 +0800 Received: (from xuemingl@localhost) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7/Submit) id w09EBfiB146307; Tue, 9 Jan 2018 22:11:41 +0800 From: Xueming Li To: Olivier MATZ , Thomas Monjalon , Jingjing Wu , Yongseok Koh Cc: Xueming Li , Shahaf Shuler , dev@dpdk.org Date: Tue, 9 Jan 2018 22:11:06 +0800 Message-Id: <20180109141110.146250-3-xuemingl@mellanox.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20180109141110.146250-1-xuemingl@mellanox.com> References: <20180109141110.146250-1-xuemingl@mellanox.com> Subject: [dpdk-dev] [PATCH 2/6] net/mlx5: allow max 192B WQE TSO inline header length X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Jan 2018 15:00:11 -0000 IPv6 VXLAN TSO and header options demands more than 128B inline header length. Signed-off-by: Xueming Li --- drivers/net/mlx5/mlx5_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 3a7706cfd..c4eea145b 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -84,7 +84,7 @@ #define MLX5_MAX_XSTATS 32 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ -#define MLX5_MAX_TSO_HEADER 128 +#define MLX5_MAX_TSO_HEADER 192 /* Default minimum number of Tx queues for vectorized Tx. */ #define MLX5_VPMD_MIN_TXQS 4 -- 2.13.3