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Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Use SPDX licence tags. examples/eventdev_pipeline_sw_pmd/main.c | 67 +------------------- .../eventdev_pipeline_sw_pmd/pipeline_common.h | 73 ++++++++++++++++++++++ 2 files changed, 75 insertions(+), 65 deletions(-) create mode 100644 examples/eventdev_pipeline_sw_pmd/pipeline_common.h diff --git a/examples/eventdev_pipeline_sw_pmd/main.c b/examples/eventdev_pipeline_sw_pmd/main.c index 111dcb0ea..2c919b7fa 100644 --- a/examples/eventdev_pipeline_sw_pmd/main.c +++ b/examples/eventdev_pipeline_sw_pmd/main.c @@ -35,73 +35,10 @@ #include #include #include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_NUM_STAGES 8 -#define BATCH_SIZE 16 -#define MAX_NUM_CORE 64 - -struct cons_data { - uint8_t dev_id; - uint8_t port_id; - uint8_t release; -} __rte_cache_aligned; - -static struct cons_data cons_data; - -struct worker_data { - uint8_t dev_id; - uint8_t port_id; -} __rte_cache_aligned; - -struct fastpath_data { - volatile int done; - uint32_t tx_lock; - uint32_t evdev_service_id; - uint32_t rxadptr_service_id; - bool rx_single; - bool tx_single; - bool sched_single; - unsigned int rx_core[MAX_NUM_CORE]; - unsigned int tx_core[MAX_NUM_CORE]; - unsigned int sched_core[MAX_NUM_CORE]; - unsigned int worker_core[MAX_NUM_CORE]; - struct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS]; -}; -static struct fastpath_data *fdata; - -struct config_data { - unsigned int active_cores; - unsigned int num_workers; - int64_t num_packets; - unsigned int num_fids; - int queue_type; - int worker_cycles; - int enable_queue_priorities; - int quiet; - int dump_dev; - int dump_dev_signal; - unsigned int num_stages; - unsigned int worker_cq_depth; - int16_t next_qid[MAX_NUM_STAGES+2]; - int16_t qid[MAX_NUM_STAGES]; - uint8_t rx_adapter_id; -}; +#include "pipeline_common.h" -static struct config_data cdata = { +struct config_data cdata = { .num_packets = (1L << 25), /* do ~32M packets */ .num_fids = 512, .queue_type = RTE_SCHED_TYPE_ATOMIC, diff --git a/examples/eventdev_pipeline_sw_pmd/pipeline_common.h b/examples/eventdev_pipeline_sw_pmd/pipeline_common.h new file mode 100644 index 000000000..1dbc01f16 --- /dev/null +++ b/examples/eventdev_pipeline_sw_pmd/pipeline_common.h @@ -0,0 +1,73 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright 2016 Intel Corporation. + * Copyright 2017 Cavium, Inc. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_NUM_STAGES 8 +#define BATCH_SIZE 16 +#define MAX_NUM_CORE 64 + +struct cons_data { + uint8_t dev_id; + uint8_t port_id; + uint8_t release; +} __rte_cache_aligned; + +struct worker_data { + uint8_t dev_id; + uint8_t port_id; +} __rte_cache_aligned; + +struct fastpath_data { + volatile int done; + uint32_t tx_lock; + uint32_t evdev_service_id; + uint32_t rxadptr_service_id; + bool rx_single; + bool tx_single; + bool sched_single; + unsigned int rx_core[MAX_NUM_CORE]; + unsigned int tx_core[MAX_NUM_CORE]; + unsigned int sched_core[MAX_NUM_CORE]; + unsigned int worker_core[MAX_NUM_CORE]; + struct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS]; +} __rte_cache_aligned; + +struct config_data { + unsigned int active_cores; + unsigned int num_workers; + int64_t num_packets; + unsigned int num_fids; + int queue_type; + int worker_cycles; + int enable_queue_priorities; + int quiet; + int dump_dev; + int dump_dev_signal; + unsigned int num_stages; + unsigned int worker_cq_depth; + int16_t next_qid[MAX_NUM_STAGES+2]; + int16_t qid[MAX_NUM_STAGES]; + uint8_t rx_adapter_id; +}; + +struct cons_data cons_data; + +struct fastpath_data *fdata; +struct config_data cdata; -- 2.15.1