From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id 0DDE91041 for ; Tue, 16 Jan 2018 01:00:12 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 9553D20C82; Mon, 15 Jan 2018 19:00:11 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute1.internal (MEProxy); Mon, 15 Jan 2018 19:00:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:date:from:message-id:subject:to:x-me-sender:x-me-sender :x-sasl-enc; s=mesmtp; bh=aGsKooQHCqYGz0MVDryQsR7k/1eIArykXokgAt u78aQ=; b=UmewHSKr+2VFKx2jhfhQehiJ75wA7a1xyA/plEuKNVdt940DUbxuuM Wd/UsReMdEIhbp3rMokt7bx+3z68ZGZ2JCjC0szyKD6I0Xv5UyLkINL9dPpArsD4 ae/iWthp5RmMVMCVW8qVZopJfnxx6IP956dRi0bDWRpZtnhmwwpTk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:message-id:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=aGsKooQHCqYGz0MVD ryQsR7k/1eIArykXokgAtu78aQ=; b=CkmIYloz32xDkma2OPSeCvBlVXHCFTOeE FqbJSIY2Di6PJU3TO3pUGPLAtIJTLDTSss5r69umFPe4O507Ttn00UgPZbv9GkcQ 2J3deMWJHSDKvo2VWWhfKr/+taZvOKPTlCFWtCUeSCxv78364U5pHOR7op7wGh0Q 2wN0x4ZytBIcoa0Jhmxem3Ajnkgs+hvoSAg+Y1vB51E0DLp5jyGrseNiKe9WMY5l 90Bv6lvDeoVr7nJ2/UVmaxuf4IeTHsWG/Pjil7XzafZZi49jOU0BYtjrmZcRilbq TQ8bEzSnID/BTju3UsQXq0X+mmUIu8HiItCbrJEduJi0oLWTD8lhw== X-ME-Sender: Received: from xps.monjalon.net (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id D9BA67E3E1; Mon, 15 Jan 2018 19:00:10 -0500 (EST) From: Thomas Monjalon To: jerin.jacob@caviumnetworks.com Cc: dev@dpdk.org Date: Tue, 16 Jan 2018 00:59:34 +0100 Message-Id: <20180115235934.16054-1-thomas@monjalon.net> X-Mailer: git-send-email 2.15.1 Subject: [dpdk-dev] [PATCH] eal/arm64: fix memory barrier macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2018 00:00:12 -0000 The macros dsb and dmb are defined as an instruction block with braces. As a consequence, when it is used in if/else without brace: if (cond) rte_mb(); else statement; the added semicolon is parsed outside of if/else, so the "else" cannot match the "if": if (cond) { asm volatile("dsb sy" : : : "memory"); } ; else statement The solution is either to use the "do { } while (0)" construct, or simply remove the braces because there is only one statement. Fixes: 84733fd0d75e ("eal/arm64: fix memory barrier definition") Signed-off-by: Thomas Monjalon --- lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h index b6bbd0b32..b012dfa74 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h @@ -15,8 +15,8 @@ extern "C" { #include "generic/rte_atomic.h" -#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); } -#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); } +#define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define rte_mb() dsb(sy) -- 2.15.1