From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <yskoh@mellanox.com> Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-he1eur01on0046.outbound.protection.outlook.com [104.47.0.46]) by dpdk.org (Postfix) with ESMTP id 065EFA48D for <dev@dpdk.org>; Tue, 16 Jan 2018 02:12:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=He8x0WydLz2UD26tPIyx7goZoZpNiV88IdTK1AJIw1I=; b=C5es1LDypBmHmkjdAsIHjuPL4DYlRVM6iXJR4l6DuEOFYoU8/PXmrjeDWd+NpDvjLX+xraBK7Mz8N8Koxsu5J3G5axoX5PgCRzmiAjV5wn1gTOIkI4KsT0psCws627Oe1xGhqL61ZBdZDwze6B4B78u/nTpRkpUOb+SLmIY735A= Received: from mellanox.com (209.116.155.178) by DB6PR0501MB2040.eurprd05.prod.outlook.com (2603:10a6:4:6::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.407.7; Tue, 16 Jan 2018 01:12:21 +0000 From: Yongseok Koh <yskoh@mellanox.com> To: adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, jerin.jacob@caviumnetworks.com, jianbo.liu@arm.com Cc: dev@dpdk.org, Yongseok Koh <yskoh@mellanox.com> Date: Mon, 15 Jan 2018 17:10:43 -0800 Message-Id: <20180116011050.18866-2-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180116011050.18866-1-yskoh@mellanox.com> References: <20171227042824.33373-1-yskoh@mellanox.com> <20180116011050.18866-1-yskoh@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [209.116.155.178] X-ClientProxiedBy: CO2PR05CA0073.namprd05.prod.outlook.com (2603:10b6:102:2::41) To DB6PR0501MB2040.eurprd05.prod.outlook.com (2603:10a6:4:6::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 07215ca1-45c0-44c1-b26a-08d55c7e3297 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; 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DB6PR0501MB2040; 6:4bmw1ALgyZ8FmfPkjxHc23x5DISyAx629spEOfwDf9CpKmwvpHG7pT2sWgn7gnWZQgKygf+IQxbH3u0XNuyS/wCgPCtdwK2fL9gEURy2u2Htl+6ToN2z89m+YuTR+Zv4odiqW4aLeZQNpDdnbJBmhY4y4oFQliUO48Vj3LJpVkHYc8g1zJNrlbSyJ9i9HZ555x+fX6Bze/qRnDqPYizOS9LpCPWfWUbpckaTAXDS8oJgAJT0tkdA8oFTVHUEhAx5JL+3CrEMEEggcgsth7+Dq9G20FegxO1jRbFbWFsanpww/ftqWkEwKjq4SbjbRQ8gIS15gfQ0LocTZsySKUd6YO5Lm3bd42m4ND03zzjCwcg=; 5:9r8cvfRvARZZW74g7VovudBZHCebowZF2aCA3SrAoR/PIB/n2q2/lz/DnBi3FQ3SqokyssS5xhxdT+wKY0ZjrzdNu577Fy+e1t4wiIKNYBkM9I0lZSmCbGljp1xu32N9KTXO/bLxqWOtnRT0pUkdLJl0oZGvev2SBfQLnMUuopE=; 24:Ru0OxVj4i7TqFlBurP1Be2vrd6IxBGZeZdYhdD8hONS1slfSI6U0SsBmILPf9bqn5jMWpHwwRlz1dR7/lrwJbLUVefB9xn5NDkoFrugo8rQ=; 7:+8eCvBE728xwQyhuuIZDxdwNSMUJoh2yMAZwy+FpRU35YbfNzZVQG4CnuU5tj1NNKgOAB8mdcdYABCRICL0wHcOCqIKZUVFGQQEWCw7mJRT1ajwI5d+Vgfr4Ma2O6m6+MBMtpxDk/TvgeYUOUTZvAFvRm/wh5Q1+f41T12yC3jRcOLdQEP2Upe7r0+Ya+uoJKc8FxbOlrjt0sg2eas+CTBP/tOc2JB3WZrM/bEXPEzmqW5xP1RkGoDMkI8NSiH52 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2018 01:12:21.4261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07215ca1-45c0-44c1-b26a-08d55c7e3297 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0501MB2040 Subject: [dpdk-dev] [PATCH v2 1/8] eal: introduce DMA memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Tue, 16 Jan 2018 01:12:24 -0000 This commit introduces rte_dma_wmb() and rte_dma_rmb(), in order to guarantee the ordering of coherent shared memory between the CPU and a DMA capable device. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> --- lib/librte_eal/common/include/generic/rte_atomic.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h index 16af5ca57..2e0503ce6 100644 --- a/lib/librte_eal/common/include/generic/rte_atomic.h +++ b/lib/librte_eal/common/include/generic/rte_atomic.h @@ -98,6 +98,24 @@ static inline void rte_io_wmb(void); */ static inline void rte_io_rmb(void); +/** + * Write memory barrier for coherent memory between lcore and IO device + * + * Guarantees that the STORE operations on coherent memory that + * precede the rte_dma_wmb() call are visible to I/O device before the + * STORE operations that follow it. + */ +static inline void rte_dma_wmb(void); + +/** + * Read memory barrier for coherent memory between lcore and IO device + * + * Guarantees that the LOAD operations on coherent memory updated by + * IO device that precede the rte_dma_rmb() call are visible to CPU + * before the LOAD operations that follow it. + */ +static inline void rte_dma_rmb(void); + #endif /* __DOXYGEN__ */ /** -- 2.11.0