From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id EF980A492 for ; Tue, 16 Jan 2018 02:54:28 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3BB193DE3F; Tue, 16 Jan 2018 01:54:28 +0000 (UTC) Received: from redhat.com (ovpn-125-221.rdu2.redhat.com [10.10.125.221]) by smtp.corp.redhat.com (Postfix) with SMTP id 8E7365D6A6; Tue, 16 Jan 2018 01:54:25 +0000 (UTC) Date: Tue, 16 Jan 2018 03:54:25 +0200 From: "Michael S. Tsirkin" To: Maxime Coquelin Cc: Konstantin Ananyev , dev@dpdk.org, Bruce Richardson Message-ID: <20180116035158-mutt-send-email-mst@kernel.org> References: <1516028971-3409-1-git-send-email-konstantin.ananyev@intel.com> <8b05f533-d146-7f97-48f4-82ddcfc3613b@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8b05f533-d146-7f97-48f4-82ddcfc3613b@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 16 Jan 2018 01:54:28 +0000 (UTC) Subject: Re: [dpdk-dev] Fwd: [PATCH v3 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2018 01:54:29 -0000 On Mon, Jan 15, 2018 at 04:15:00PM +0100, Maxime Coquelin wrote: > Hi Michael, > > FYI: > > -------- Forwarded Message -------- > Subject: [dpdk-dev] [PATCH v3 2/2] eal/x86: Use lock-prefixed instructions > to reduce cost of rte_smp_mb() > Date: Mon, 15 Jan 2018 15:09:31 +0000 > From: Konstantin Ananyev > To: dev@dpdk.org > CC: Konstantin Ananyev > > On x86 it is possible to use lock-prefixed instructions to get > the similar effect as mfence. > As pointed by Java guys, on most modern HW that gives a better > performance than using mfence: > https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > That patch adopts that technique for rte_smp_mb() implementation. > On BDW 2.2 mb_autotest on single lcore reports 2X cycle reduction, > i.e. from ~110 to ~55 cycles per operation. > > Signed-off-by: Konstantin Ananyev > Acked-by: Bruce Richardson > --- > .../common/include/arch/x86/rte_atomic.h | 44 > +++++++++++++++++++++- > 1 file changed, 42 insertions(+), 2 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h > b/lib/librte_eal/common/include/arch/x86/rte_atomic.h > index 8469f97e1..9d466d94a 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h > @@ -26,12 +26,52 @@ extern "C" { > #define rte_rmb() _mm_lfence() > -#define rte_smp_mb() rte_mb() > - > #define rte_smp_wmb() rte_compiler_barrier() > #define rte_smp_rmb() rte_compiler_barrier() > +/* > + * From Intel Software Development Manual; Vol 3; > + * 8.2.2 Memory Ordering in P6 and More Recent Processor Families: > + * ... > + * . Reads are not reordered with other reads. > + * . Writes are not reordered with older reads. > + * . Writes to memory are not reordered with other writes, > + * with the following exceptions: > + * . streaming stores (writes) executed with the non-temporal move > + * instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and > + * . string operations (see Section 8.2.4.1). > + * ... > + * . Reads may be reordered with older writes to different locations but > not > + * with older writes to the same location. > + * . Reads or writes cannot be reordered with I/O instructions, > + * locked instructions, or serializing instructions. > + * . Reads cannot pass earlier LFENCE and MFENCE instructions. > + * . Writes ... cannot pass earlier LFENCE, SFENCE, and MFENCE > instructions. > + * . LFENCE instructions cannot pass earlier reads. > + * . SFENCE instructions cannot pass earlier writes ... > + * . MFENCE instructions cannot pass earlier reads, writes ... > + * > + * As pointed by Java guys, that makes possible to use lock-prefixed > + * instructions to get the same effect as mfence and on most modern HW > + * that gives a better perfomance then using mfence: > + * https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > + * Basic idea is to use lock prefixed add with some dummy memory location > + * as the destination. From their experiments 128B(2 cache lines) below > + * current stack pointer looks like a good candidate. > + * So below we use that techinque for rte_smp_mb() implementation. > + */ > + > +static __rte_always_inline void > +rte_smp_mb(void) > +{ > +#ifdef RTE_ARCH_I686 > + asm volatile("lock addl $0, -128(%%esp); " ::: "memory"); > +#else > + asm volatile("lock addl $0, -128(%%rsp); " ::: "memory"); > +#endif > +} > + > #define rte_io_mb() rte_mb() > #define rte_io_wmb() rte_compiler_barrier() In my testing this appears to be suboptimal when the calling function is large. The following seems to work better: +static __rte_always_inline void +rte_smp_mb(void) +{ +#ifdef RTE_ARCH_I686 + asm volatile("lock addl $0, -132(%%esp); " ::: "memory"); +#else + asm volatile("lock addl $0, -132(%%rsp); " ::: "memory"); +#endif +} + The reason most likely is that 128 still overlaps the x86 red zone by 4 bytes. Feel free to reuse, and add Signed-off-by: Michael S. Tsirkin > -- > 2.13.6