From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 07F144C8F for ; Tue, 6 Mar 2018 12:59:51 +0100 (CET) Received: by mail-wm0-f67.google.com with SMTP id s206so17671453wme.0 for ; Tue, 06 Mar 2018 03:59:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=cLNrdKMvUuWh5nTqHEvfBR4uCRfPBmc7HfDiO37gPTk=; b=SCsPnDx5GYIiNnxecRgSIWJwPGEB7WTggUxqxYub7vUh2U1ab8dTnNvWt57TjRXqAW kD1/8Rcf7sCar79eMj3NCgfalprN3hxuAdGmWMqxbeD0ypWBDMCLCgMtm051Hu2xyzni YelUDmY/AFs65ImH8BIbXSqiEBZuDM3f4RbWhROsaOVpDWg502tbcV3t4cCFH/fNp41A 78H7sdgSyEXiNV3VtIIMH21WXvvhm4oy4g8NIRIWNbbM85jWpCNzmbvExKdxBt3miL+r aWxzNUEBtguaaCiRwagM7ndKVC7O56oUbEUzAuU+tWTwWQD44x/32FL9IiX6sjNApfUZ voig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=cLNrdKMvUuWh5nTqHEvfBR4uCRfPBmc7HfDiO37gPTk=; b=t+4CCaX5ivMT0YUz6OvbEhbUTQdoXdGc/XB36rYlD62LFy6dT7iCAvQoUOxX8ddFBf im0DrBvtzXX7lmbqL1y1pfmRjfqHtC+X4m+Uis7i98q3wEqgGQiz9m/iSghOP7A1umBS Wt9X1NXnJj7G89+3MqTcrRMGv4boD/BI9aoY3x3nkU/EIin8uiOoebrA26v7Vjb95XJb NP60ayz6j+K27dVT7lfa7wnIbybS2/teApxqmywJBDeEs+TWKablQWcwNluUyDZ2tqnz FlWCQCkMpl64Z4f7EhAV+tm9EjSeDx2YYYVZ8PF2+TdJFuOkLKJI4lc2TKHVHFwOiKUK fqtg== X-Gm-Message-State: AElRT7GVV1bGebhxG/1Uiv2r/EsSk4NOde2vU9vZT/1k5J9uahFFaEOp hxPYdp6kPsPGaixbNh5YjlgBvALE X-Google-Smtp-Source: AG47ELtY4XvXnhXBRQHUoh5rR9KG/xeBv7EfLbCmv2fhuKUuUzUqFFZsiBJ9BwYvDLnEpGxsDjyt6g== X-Received: by 10.28.22.210 with SMTP id 201mr7061423wmw.66.1520337591333; Tue, 06 Mar 2018 03:59:51 -0800 (PST) Received: from bidouze.vm.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id y64sm34568594wrb.56.2018.03.06.03.59.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Mar 2018 03:59:50 -0800 (PST) Date: Tue, 6 Mar 2018 12:59:37 +0100 From: =?iso-8859-1?Q?Ga=EBtan?= Rivet To: Bruce Richardson Cc: "Xu, Rosen" , Shreyansh Jain , "dev@dpdk.org" , "Doherty, Declan" , "Zhang, Tianfei" Message-ID: <20180306115937.7zxzhzihbgcnhgaz@bidouze.vm.6wind.com> References: <1520300638-134954-1-git-send-email-rosen.xu@intel.com> <1520300638-134954-4-git-send-email-rosen.xu@intel.com> <0E78D399C70DA940A335608C6ED296D739F0ED23@SHSMSX104.ccr.corp.intel.com> <20180306104622.3ngsn6syickaphbm@bidouze.vm.6wind.com> <20180306113616.GA7644@bricha3-MOBL3.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180306113616.GA7644@bricha3-MOBL3.ger.corp.intel.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Mar 2018 11:59:52 -0000 On Tue, Mar 06, 2018 at 11:36:17AM +0000, Bruce Richardson wrote: > On Tue, Mar 06, 2018 at 11:46:22AM +0100, Gaëtan Rivet wrote: > > On Tue, Mar 06, 2018 at 10:42:14AM +0000, Xu, Rosen wrote: > > > > > > > > > -----Original Message----- > > > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > > > Sent: Tuesday, March 06, 2018 14:20 > > > To: Xu, Rosen > > > Cc: dev@dpdk.org; Doherty, Declan ; Zhang, Tianfei > > > Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus > > > > > > On Tue, Mar 6, 2018 at 7:13 AM, Rosen Xu wrote: > > > > Signed-off-by: Rosen Xu > > > > --- > > > > lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++- > > > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/lib/librte_eal/common/eal_common_bus.c > > > > b/lib/librte_eal/common/eal_common_bus.c > > > > index 3e022d5..74bfa15 100644 > > > > --- a/lib/librte_eal/common/eal_common_bus.c > > > > +++ b/lib/librte_eal/common/eal_common_bus.c > > > > @@ -70,15 +70,27 @@ struct rte_bus_list rte_bus_list = > > > > rte_bus_scan(void) > > > > { > > > > int ret; > > > > - struct rte_bus *bus = NULL; > > > > + struct rte_bus *bus = NULL, *ifpga_bus = NULL; > > > > > > > > TAILQ_FOREACH(bus, &rte_bus_list, next) { > > > > + if (!strcmp(bus->name, "ifpga")) { > > > > + ifpga_bus = bus; > > > > + continue; > > > > + } > > > > + > > > > ret = bus->scan(); > > > > if (ret) > > > > RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n", > > > > bus->name); > > > > } > > > > > > > > + if (ifpga_bus) { > > > > + ret = ifpga_bus->scan(); > > > > + if (ret) > > > > + RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n", > > > > + ifpga_bus->name); > > > > + } > > > > + > > > > > > You are doing this just so that PCI scans are completed *before* ifpga scans? > > > Rosen: yes > > > Well, I understand that this certainly is an issue that we can't yet define a priority ordering of bus scans. > > > > > > But, I think what you are require is a simpler: > > > > > > In the file ifpga_bus.c: > > > > > > +RTE_REGISTER_BUS(IFPGA_BUS_NAME, rte_ifpga_bus.bus); <== this > > > ... > > > ... > > > #define RTE_REGISTER_BUS(nm, bus) \ > > > RTE_INIT_PRIO(businitfn_ ##nm, 110); \ > > > > > > If you define your own version of RTE_REGISTER_BUS with the priority number higher, it would be inserted later in the bus list. > > > rte_register_bus doesn't do any inherent ordering. > > > This would save the changes you are doing in the lib/librte_eal/common/eal_common_bus.c file. > > > > > > But I think there has to be a better provision of defining priority of bus scans - I am sure when new devices come in, there would be possibility of dependencies as in your case. > > > Rosen: is the priority scan of bus is implemented? > > > > No, there is no priority set for scanning order. > > However, the order in which buses are registered, will modify the order > > in which scans are done. > > > > Thus, if you change the priority of your registration, you should be > > able to ensure that your scan comes last. > > > > Can we register the bus only when a PCI device match is found at > runtime, e.g. as part of the PCI driver instance initialization? > > /Bruce Technically, yes. You would append a new bus during rte_bus_probe, so the linked list would simply have a new node and you would then probe it. You would need to make sure you scan your bus first, so you would have some weird conditions (whether you are loaded during probe or naturally, you'd have to do your scan or not). However, this seems like a terrible idea. You introduce an edge case that will need to be carried over in most of the bus API implementation. This new bus seems like a specialization of the PCI bus. Why not directly use the PCI bus and have your driver linked to either a rawdev or a vdev, where you could store your metadata and expose a specialized interface? -- Gaëtan Rivet 6WIND