From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0083.outbound.protection.outlook.com [104.47.38.83]) by dpdk.org (Postfix) with ESMTP id A6F09A496 for ; Wed, 14 Mar 2018 14:53:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=nv5fdUPhHSZzdA4k2iywJxKKTZHyUyp43y9r6SQ7jCQ=; b=M4uYKHr0PDzh8NJR1tiJplQnnpz/RL48jKsZNDxs7Tshfho85eUcPZxVhs8PNA19bOCr8nC8l5hbs30PJDhmCDzOxQ/mteWnwMWEloQ2MHIczjtJJ5Lru84QbxesGvEDhbYE9zMqwQbwLzBsfVxPndGokYTFkw7xLfDBkeYFeDo= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Pavan.Bhagavatula@cavium.com; Received: from ltp-pvn.caveonetworks.com (111.93.218.67) by MWHPR07MB3470.namprd07.prod.outlook.com (2603:10b6:301:63::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.567.14; Wed, 14 Mar 2018 13:53:14 +0000 From: Pavan Nikhilesh To: jerin.jacob@caviumnetworks.com, santosh.shukla@caviumnetworks.com, erik.g.carrillo@intel.com Cc: dev@dpdk.org, Pavan Nikhilesh Date: Wed, 14 Mar 2018 19:22:25 +0530 Message-Id: <20180314135233.31282-4-pbhagavatula@caviumnetworks.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180314135233.31282-1-pbhagavatula@caviumnetworks.com> References: <20180216213700.3415-1-pbhagavatula@caviumnetworks.com> <20180314135233.31282-1-pbhagavatula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: DM5PR20CA0005.namprd20.prod.outlook.com (2603:10b6:3:93::15) To MWHPR07MB3470.namprd07.prod.outlook.com (2603:10b6:301:63::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 83c1d7fe-069b-46c6-89de-08d589b2efe4 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(5600026)(4604075)(2017052603328)(7153060)(7193020); SRVR:MWHPR07MB3470; X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3470; 3:1MYT/+PwzE39Tup8eJRIj/6ltLVm338Ky9PzhFu5Cg0PxW6riJyG7YFnWJSkeu6mdAOXVp+yO/nOE3lu5COuPlxH7AClNjUy4Vweqh5UYUZk8kKwwB7ggnnpbiXQU7IQiQfkwv3pfii8UY7tsXGGuoeqZHDI9Cj1mM3pC0W2n7NzilY6OLm0KO8uQhAEFMQerIC/KsE6yESPA9fHb43F0C0ZsL38/fRvI5iAGXdlRso/3dXPLaRjrW3c6svAjHKS; 25:ACAg6SJKyW33CZZEakYluChDuskBWeFZy9tDnmyzX+q+80iVA6NUfJmg57uorMm0iPij/QpXZR46mv1zVoo17yGD1scJr76xyct4V2AA35ENkk1zB29g2HZNB3qhQJrQMIr70cbRjwIVXNhcBknJFkj4o6hSO4cWVu2OdNKYcodPP4YSgHBsXpvqJbcyRyJI+c+Pz1uEkXG9KV2cEWJ+A/D7YiU1yjasBcbdpKoSm+KMSXOvNgKBiEQ81jKWaNmUBkjAp+qvj74gQko5MWCR8KNF0CzXQX8vS8wXzXsWOjU8nGX+Ah7ulYRDTdGsY5nvScmkQmY1SvIc/KBxJbfNCA==; 31:IkatHLytAWTJEimx9zCvjxd2GRlCIwQs8CZFrYw+QU7qBCi4OBCzW4+uNXtMrbtKWHnPczL+UpFwGyQ5I6OAPFFG2lgY31Azj8u3HuWUi9/CaZkFb0x9CauHs7TUWRszvp6v/CQ6YUM0rGnI9xtOhMRyJStA283EKlD6R5mntLXxhPanxR97ue8/q9I/mhT7kzW/aV+4ki9VJ4YxKZuwFEdlFFZqe1KJePy5Uz96+Ks= X-MS-TrafficTypeDiagnostic: MWHPR07MB3470: X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3470; 20:mU3JjH+BGwadqwRgxwl5YonIggTOWWTwp6ePTT2E0CbaenK7M8mGVcmyqNaH4SI30dCr2Oy23QaFrexS4yTUnnX8oZeuVAyCW8whHOWeZoX7c/tcle6A6QxxFyXwbF+1wHHfGNUeuGgqQvceJx3EA1mkEdGMm5OqHRR//PzoTc8DquvkZzcQ7uGlDEK0qoYAQGZH0NK5BEWpenOWjhW1KWd0Zbt1nSlYPbwXuPnDg9X1k6cBsh7pVYrjaaGIceZtDYAHCS+MlY6t9Wq7ITZmYNSM0ZfbhxYeiJT2SYEvraE/RPVVjQ6KalqnQERcuJtLzGGE2qUyo55fkvE3ybfCo+57QqhtUBnvcQtGtVNvS2MJUjjO3l2u8TZsXhc19ho2MviuiDos2Xv3cbjxfmSbEUYUBwE3Tx4grWQEJqGRjtxOmpqJWX2eFnE4WUFCoMV1v/Xsd/oZXtIxNKEs2hmSchbjN034X1QXZNxeGf14dm2L3oh0TuJzuDxy9GryFe4Qz9ug52DPEaBv1BE6VYmeF6ytP+zNV/Rzc6H6ShPajT4OdRt7X9q2yXN5dc1DLW2OBgBIVMeMjP7bhClRonpPfHJlYFvk549Z5x3XokdewEw=; 4:xd+2Wdqe86pSx2sAlrwg9WlXHOBoDu6F5OPwbnDwY3lvNjVkrlnDjIgCVsxcwGpM/1ZcQBzhhS64Io0garnQTnPmBOrW5pOp28XttE/RXw4vvcSYsfo2UzXByaQ8Plqty7h81FrqjIeFEYUcTY9uHxkxnN3AWQpsLVorSzwWGHpEMOw3xu9TKdc6OSJVUpiwa6p9ghlqbseDX1yVRKyixjJ6LYy/2n5oHK1372YQ+MG4VRe/vmUW93PD2BguycZxS4NgYZwD/sncj8WvVP2/6A== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231221)(944501244)(52105095)(3002001)(93006095)(10201501046)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123562045)(20161123560045)(20161123558120)(6072148)(201708071742011); SRVR:MWHPR07MB3470; BCL:0; PCL:0; RULEID:; SRVR:MWHPR07MB3470; X-Forefront-PRVS: 0611A21987 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(376002)(39860400002)(39380400002)(366004)(346002)(396003)(189003)(199004)(53936002)(6512007)(3846002)(4326008)(6666003)(6506007)(48376002)(26005)(105586002)(68736007)(97736004)(47776003)(2950100002)(386003)(1076002)(6486002)(106356001)(52116002)(305945005)(107886003)(7736002)(69596002)(76176011)(66066001)(5660300001)(59450400001)(51416003)(25786009)(36756003)(50466002)(316002)(16586007)(72206003)(53416004)(1857600001)(6116002)(478600001)(8676002)(81156014)(81166006)(42882007)(2906002)(5009440100003)(50226002)(16526019)(8936002)(42262002); DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3470; H:ltp-pvn.caveonetworks.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; MWHPR07MB3470; 23:hHBtxDOdGE+rVdXMC4J9nnKUEeNiv5CFhN0jM4OAZ?= =?us-ascii?Q?C3ZwwqX07gcM+Z6mzXKhPF4+tPSUxjErKC6GcnQEwugrjFnL3td+Zu0oezhP?= =?us-ascii?Q?da+/Y8/6pJfyrSHRfEqA7VV+DQVWlK++ENnamxWhaL8oLsQZmMd46ue7mXMK?= =?us-ascii?Q?jWHFVlqL80NFzJM39QD8DYbaK6vnpnoBJLgz5Cz5ug8YSVGbMCS2nvsQxaae?= =?us-ascii?Q?5e9OfIGJBkdaOYV4CbiDLpVYNrx6n+ThUGAXXxLXNxu+Vp1Sl9rIWjmmyyZZ?= =?us-ascii?Q?pxhnExRPtnIhI3AdbiKuiAUiRRHO9aDrJOSPdQWooFm/z1ADUrJMzkVtYTgi?= =?us-ascii?Q?Iv89xZ8BZfyZnkHGQuLuVWwUbJ+fWoIqyrysyC+heTWaqumKrQPZ1b06fRUP?= =?us-ascii?Q?PyFDNaqtDTcmAe1k/Ii39Toy6P62DcPnyOAJzDib9+3O0lJIhrY9H+RpKRHx?= =?us-ascii?Q?lXN70Tm4vsiTWmedqg/d29oO6UZuAQQbJ8LHTamSoEWxJhNVsFK9MEdM0OAJ?= =?us-ascii?Q?0LgkTULEPLWnZo+XzEhm5T/ad0RA/BMTmEtT82BJQrJeU5/jhb/b7hGN31BW?= =?us-ascii?Q?g7YQRE+qgX4yd/7uKp8qlV8n+0QPI4DMYjrcIXTOz+H9RGjWQHc74KdozSId?= =?us-ascii?Q?J6M89/NLSomJSSSX/RepinscXNBIN1JlQj6bkimZxFU2f2S3sdgZHWLOgezd?= =?us-ascii?Q?AB1SQeiDEfcz5CgpqQpmA06840GUgLwgihWhCJuapFLjbVkZCByYWw3H/Z3i?= =?us-ascii?Q?I26DInQF6KY/Y41CNL7KVtysraDFLv2Md8J8NQs27Xh9Xw5h0eDJFRoaJPJo?= =?us-ascii?Q?wt6TlU8SJ7yYy/BWslmxKzT1VnxloqasDHzRggyXlin6Og/hXSkeO+UE35XX?= =?us-ascii?Q?LuTrvMokWpN6d9Lmzgv4zY2iP0f7TQ/Z/GqBdaAun865B/7+BwjGsLdoPlC9?= =?us-ascii?Q?xy5J0rHtbLv7geOOEsX2/S7eKfA3YImNi5GwlAXW/sIUFZXINuDguVGldHyt?= =?us-ascii?Q?jDRr1g0Jt8gajQCGe1QxqJ/V3BVGW2iZU0/kQLsChCaQod+VM5sGVMOfKhbO?= =?us-ascii?Q?TzArnZ2cV0lcLn7HN5e3MhTRO3DaMxTuyQoBNETi5qV41NEXxqikYtbL8vti?= =?us-ascii?Q?U22Jlrol9c30zBkIdR7vipHsWIQyX/vmLFAaMfHNG7UrB9Ie0WbnrHGHUmBn?= =?us-ascii?Q?E8/e7vfJ5xW5HC4E3+pOk2QSCDDxpTpV+6+L4qYfljqD71Y97cZmQZ0vo+Of?= =?us-ascii?Q?/LP3J3lZqpL6phHTfN9CqlTiX8SIfTJAzzVKF4h?= X-Microsoft-Antispam-Message-Info: moOsKag4nRHJSwd0pwdQVBvlKZaWc99h9owF9q4iwCy6pmpgCdMkUs9z5uzDQXTF8NlFysMF3tY415eYoCvwTjH5fg8c/zwRXB+ZnRpciWFYFBL5Er+ZiI7b6/NZ9/8X4pdhazaWXceBr2Xa9m3j5k+4sX7KxxTNr2Qg6kDMqAUbbH6az55zNwLUUKV9kRnX X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3470; 6:A145SzshBqHcX/mWu/3FKgCk8eXWzNqLL4zeg5ASgrPawfu9Gm33G+d1bHxbV67j+br9elzTfaKwMaqLr5MaDP+pjU0ac35KkfMnSboJIwM9yI4kPKk1TlUglMgtTnO1U7w0UJUJjQNxfdb+LuC8U23vbhs4UVkS/4JJFzey9aKgagI4ZKyuz0t3snellW1+P/tiHuUBT+KwkytQOsfzq+Y65uiiJodnJNo7ndcgthFtDsNZefhyb5FIQMm72p4EjB+u25lqToyWVIzAfSx7EeOARBFOMTGMcF+Tkc1XHgeZEVh3NNLfvC7V4yrwD0F0XDWMTmqaQac82qg94yUG3EXxwKAQPb7bgyYcwaxG+pw=; 5:jtqHdwEj+LeIIFyx3FafhQ7geb3DbQ7Yd2OIdMjo9CL9C87enWmh4lcqpJDsTzEd5G4gsAZEyUt1bDEpvnsN+Nia2UKoa0ieyrK2HjVZ6ia+sZj0jWpmJ/CwLDvRSX3FbRN/4C30UOu/7YVlANOe9WWiaZMn+HMe4f6JWup6Yt4=; 24:JEBkVSIygjDo/7dSYOwyB0fiICwL+PUq0OOq+HSt3A1UbRk9NStlkBeAWC3Ho/QLPanio34Xy7T7qCpJTQuKPtaSHM9eBY9dkADQJSmNM4E=; 7:BiEAOVonm5HCETZOZw6gk+77ioWAhJLXPgjVrvUVgEBBIRdfznyLfCqeaGoWlY7UDBb9Air0sUN6cvkHEf44BtllhfEd8kJLumh3RTyQtIyufywFGwlHKP+3E1KAsImaBJS8gSpGtZASTuUjE/06hNt99AfQ+TpAKGmSyPI3PHQZi9hE4dwka2NjQNZfviZnSmU95zK3+M+253aMAx2E2QxE/z5g+r/CtPcImLenhUj6KWu4OhX7fKSUxT30x7Ch SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2018 13:53:14.4708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83c1d7fe-069b-46c6-89de-08d589b2efe4 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR07MB3470 Subject: [dpdk-dev] [PATCH v2 03/11] event/octeontx: add support to create and free timer adapter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Mar 2018 13:53:19 -0000 When the application requests to create a timer device, Octeontx TIM create does the following: - Get the requested TIMvf ring based on adapter_id. - Verify the config parameters supplied. - Allocate memory required for * Buckets based on min and max timeout supplied. * Allocate the chunk pool based on the number of timers. - Clear the interrupts. On Free: - Free the allocated bucket and chunk memory. - Free private data used by TIMvf. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx/Makefile | 2 + drivers/event/octeontx/meson.build | 3 +- drivers/event/octeontx/ssovf_evdev.c | 3 + drivers/event/octeontx/timvf_evdev.c | 161 ++++++++++++++++++++++++++++++++++ drivers/event/octeontx/timvf_evdev.h | 165 +++++++++++++++++++++++++++++++++++ 5 files changed, 333 insertions(+), 1 deletion(-) create mode 100644 drivers/event/octeontx/timvf_evdev.c create mode 100644 drivers/event/octeontx/timvf_evdev.h diff --git a/drivers/event/octeontx/Makefile b/drivers/event/octeontx/Makefile index 0e49efd84..570a79412 100644 --- a/drivers/event/octeontx/Makefile +++ b/drivers/event/octeontx/Makefile @@ -12,6 +12,7 @@ LIB = librte_pmd_octeontx_ssovf.a CFLAGS += $(WERROR_FLAGS) CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx/ CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx/ +CFLAGS += -DALLOW_EXPERIMENTAL_API LDLIBS += -lrte_eal -lrte_eventdev -lrte_mempool_octeontx -lrte_pmd_octeontx LDLIBS += -lrte_bus_pci -lrte_mempool -lrte_mbuf -lrte_kvargs @@ -27,6 +28,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_worker.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev_selftest.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += timvf_evdev.c ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y) CFLAGS_ssovf_worker.o += -fno-prefetch-loop-arrays diff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build index 358fc9fc9..8941f8a56 100644 --- a/drivers/event/octeontx/meson.build +++ b/drivers/event/octeontx/meson.build @@ -3,7 +3,8 @@ sources = files('ssovf_worker.c', 'ssovf_evdev.c', - 'ssovf_evdev_selftest.c' + 'ssovf_evdev_selftest.c', + 'timvf_evdev.c', ) deps += ['mempool_octeontx', 'bus_vdev', 'pmd_octeontx'] diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c index a1086077d..54384d465 100644 --- a/drivers/event/octeontx/ssovf_evdev.c +++ b/drivers/event/octeontx/ssovf_evdev.c @@ -18,6 +18,7 @@ #include #include "ssovf_evdev.h" +#include "timvf_evdev.h" int otx_logtype_ssovf; @@ -610,6 +611,8 @@ static const struct rte_eventdev_ops ssovf_ops = { .eth_rx_adapter_start = ssovf_eth_rx_adapter_start, .eth_rx_adapter_stop = ssovf_eth_rx_adapter_stop, + .timer_adapter_caps_get = timvf_timer_adapter_caps_get, + .dev_selftest = test_eventdev_octeontx, .dump = ssovf_dump, diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c new file mode 100644 index 000000000..473311fa4 --- /dev/null +++ b/drivers/event/octeontx/timvf_evdev.c @@ -0,0 +1,161 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "timvf_evdev.h" + +int otx_logtype_timvf; + +RTE_INIT(otx_timvf_init_log); +static void +otx_timvf_init_log(void) +{ + otx_logtype_timvf = rte_log_register("pmd.event.octeontx.timer"); + if (otx_logtype_timvf >= 0) + rte_log_set_level(otx_logtype_timvf, RTE_LOG_NOTICE); +} + +static void +timvf_ring_info_get(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer_adapter_info *adptr_info) +{ + struct timvf_ring *timr = adptr->data->adapter_priv; + adptr_info->max_tmo_ns = timr->max_tout; + adptr_info->min_resolution_ns = timr->tck_nsec; + rte_memcpy(&adptr_info->conf, &adptr->data->conf, + sizeof(struct rte_event_timer_adapter_conf)); +} + +static int +timvf_ring_create(struct rte_event_timer_adapter *adptr) +{ + char pool_name[25]; + int ret; + uint64_t nb_timers; + struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; + struct timvf_ring *timr; + struct octeontx_timvf_info tinfo; + const char *mempool_ops; + + if (octeontx_timvf_info(&tinfo) < 0) + return -ENODEV; + + if (adptr->data->id >= tinfo.total_timvfs) + return -ENODEV; + + timr = rte_zmalloc("octeontx_timvf_priv", + sizeof(struct timvf_ring), 0); + if (timr == NULL) + return -ENOMEM; + + adptr->data->adapter_priv = timr; + /* Check config parameters. */ + if ((rcfg->clk_src != RTE_EVENT_TIMER_ADAPTER_EXT_CLK0) && + (!rcfg->timer_tick_ns || + rcfg->timer_tick_ns < TIM_MIN_INTERVAL)) { + timvf_log_err("Too low timer ticks"); + goto cfg_err; + } + + switch (rcfg->clk_src) { + case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: + timr->clk_src = TIM_CLK_SRC_SCLK; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0: + timr->clk_src = TIM_CLK_SRC_GPIO; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1: + timr->clk_src = TIM_CLK_SRC_GTI; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2: + timr->clk_src = TIM_CLK_SRC_PTP; + break; + default: + timvf_log_err("Invalid clk source specified."); + goto cfg_err; + } + + timr->tim_ring_id = adptr->data->id; + timr->tck_nsec = rcfg->timer_tick_ns; + timr->max_tout = rcfg->max_tmo_ns; + timr->meta.nb_bkts = (timr->max_tout / timr->tck_nsec) + 1; + timr->vbar0 = octeontx_timvf_bar(timr->tim_ring_id, 0); + timr->bkt_pos = (uint8_t *)timr->vbar0 + TIM_VRING_REL; + nb_timers = rcfg->nb_timers; + timr->meta.get_target_bkt = bkt_mod; + + timr->nb_chunks = nb_timers / nb_chunk_slots; + + timr->meta.bkt = rte_zmalloc("octeontx_timvf_bucket", + (timr->meta.nb_bkts) * sizeof(struct tim_mem_bucket), + 0); + if (timr->meta.bkt == NULL) + goto mem_err; + + snprintf(pool_name, 30, "timvf_meta.chunk_pool%d", timr->tim_ring_id); + timr->meta.chunk_pool = (void *)rte_mempool_create_empty(pool_name, + timr->nb_chunks, TIM_CHUNK_SIZE, 0, 0, rte_socket_id(), + 0); + + if (!timr->meta.chunk_pool) { + rte_free(timr->meta.bkt); + timvf_log_err("Unable to create chunkpool."); + return -ENOMEM; + } + + mempool_ops = rte_mbuf_best_mempool_ops(); + ret = rte_mempool_set_ops_byname(timr->meta.chunk_pool, + mempool_ops, NULL); + + if (ret != 0) { + timvf_log_err("Unable to set chunkpool ops."); + goto mem_err; + } + + ret = rte_mempool_populate_default(timr->meta.chunk_pool); + if (ret < 0) { + timvf_log_err("Unable to set populate chunkpool."); + goto mem_err; + } + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VRING_BASE); + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT); + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT_W1S); + timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1C); + timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1S); + + return 0; +mem_err: + rte_free(timr); + return -ENOMEM; +cfg_err: + rte_free(timr); + return -EINVAL; +} + +static int +timvf_ring_free(struct rte_event_timer_adapter *adptr) +{ + struct timvf_ring *timr = adptr->data->adapter_priv; + rte_mempool_free(timr->meta.chunk_pool); + rte_free(timr->meta.bkt); + rte_free(adptr->data->adapter_priv); + return 0; +} + +static struct rte_event_timer_adapter_ops timvf_ops = { + .init = timvf_ring_create, + .uninit = timvf_ring_free, + .get_info = timvf_ring_info_get, +}; + +int +timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, const struct rte_event_timer_adapter_ops **ops) +{ + RTE_SET_USED(dev); + RTE_SET_USED(flags); + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *ops = &timvf_ops; + return -EINVAL; +} diff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h new file mode 100644 index 000000000..e3f558e10 --- /dev/null +++ b/drivers/event/octeontx/timvf_evdev.h @@ -0,0 +1,165 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __TIMVF_EVDEV_H__ +#define __TIMVF_EVDEV_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define timvf_log(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \ + "[%s] %s() " fmt "\n", \ + RTE_STR(event_timer_octeontx), __func__, ## args) + +#define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__) +#define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__) +#define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__) +#define timvf_func_trace timvf_log_dbg + +#define TIM_COPROC (8) +#define TIM_GET_DEV_INFO (1) +#define TIM_GET_RING_INFO (2) +#define TIM_SET_RING_INFO (3) +#define TIM_RING_START_CYC_GET (4) + +#define TIM_MAX_RINGS (64) +#define TIM_DEV_PER_NODE (1) +#define TIM_VF_PER_DEV (64) +#define TIM_RING_PER_DEV (TIM_VF_PER_DEV) +#define TIM_RING_NODE_SHIFT (6) +#define TIM_RING_MASK ((TIM_RING_PER_DEV) - 1) +#define TIM_RING_INVALID (-1) + +#define TIM_MIN_INTERVAL (1E3) +#define TIM_MAX_INTERVAL ((1ull << 32) - 1) +#define TIM_MAX_BUCKETS (1ull << 20) +#define TIM_CHUNK_SIZE (4096) +#define TIM_MAX_CHUNKS_PER_BUCKET (1ull << 32) + +#define TIMVF_MAX_BURST (8) + +/* TIM VF Control/Status registers (CSRs): */ +/* VF_BAR0: */ +#define TIM_VF_NRSPERR_INT (0x0) +#define TIM_VF_NRSPERR_INT_W1S (0x8) +#define TIM_VF_NRSPERR_ENA_W1C (0x10) +#define TIM_VF_NRSPERR_ENA_W1S (0x18) +#define TIM_VRING_FR_RN_CYCLES (0x20) +#define TIM_VRING_FR_RN_GPIOS (0x28) +#define TIM_VRING_FR_RN_GTI (0x30) +#define TIM_VRING_FR_RN_PTP (0x38) +#define TIM_VRING_CTL0 (0x40) +#define TIM_VRING_CTL1 (0x50) +#define TIM_VRING_CTL2 (0x60) +#define TIM_VRING_BASE (0x100) +#define TIM_VRING_AURA (0x108) +#define TIM_VRING_REL (0x110) + +#define timvf_read64 rte_read64_relaxed +#define timvf_write64 rte_write64_relaxed + +#ifndef __hot +#define __hot __attribute__((hot)) +#endif + +extern int otx_logtype_timvf; + +static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1; + +enum timvf_clk_src { + TIM_CLK_SRC_SCLK, + TIM_CLK_SRC_GPIO, + TIM_CLK_SRC_GTI, + TIM_CLK_SRC_PTP, +}; + +/* TIM_MEM_BUCKET */ +struct tim_mem_bucket { + uint64_t first_chunk; + union { + uint64_t w1; + struct { + uint32_t nb_entry; + uint8_t sbt:1; + uint8_t hbt:1; + uint8_t bsk:1; + uint8_t rsvd:5; + uint8_t lock; + int16_t chunk_remainder; + }; + }; + uint64_t current_chunk; + uint64_t pad; +} __rte_packed; + +struct tim_mem_entry { + uint64_t w0; + uint64_t wqe; +} __rte_packed; + +struct timvf_ctrl_reg { + uint64_t rctrl0; + uint64_t rctrl1; + uint64_t rctrl2; + uint8_t use_pmu; +} __rte_packed; + +struct timvf_ring; + +typedef uint32_t (*bkt_id)(const uint32_t bkt_tcks, const uint32_t nb_bkts); +typedef struct tim_mem_entry * (*refill_chunk)( + struct tim_mem_bucket * const bkt, + struct timvf_ring * const timr); + +struct timvf_meta { + bkt_id get_target_bkt; + refill_chunk refill_chunk; + struct rte_reciprocal_u64 fast_div; + uint64_t ring_start_cyc; + uint32_t nb_bkts; + struct tim_mem_bucket *bkt; + void *chunk_pool; + uint64_t tck_int; +}; + +struct timvf_ring { + struct timvf_meta meta; + uint64_t tck_nsec; + void *vbar0; + void *bkt_pos; + uint64_t max_tout; + uint64_t nb_chunks; + enum timvf_clk_src clk_src; + uint16_t tim_ring_id; +} __rte_cache_aligned; + +static __rte_always_inline uint32_t +bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts) +{ + return rel_bkt % nb_bkts; +} + +int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); + +#endif /* __TIMVF_EVDEV_H__ */ -- 2.16.2