From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 0D30434F0 for ; Tue, 20 Mar 2018 15:59:09 +0100 (CET) Received: by mail-wm0-f67.google.com with SMTP id l16so4133643wmh.3 for ; Tue, 20 Mar 2018 07:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=tlDkgcE659mvNUmUK6Dqv+T/1aYYlHB/6ptv/S4T04c=; b=rB56HpUl6jzqKJ9PZUKj5igUvHQT6ITvrgAMLft8XhxnVek0YESl+h3ysga1dPrSzU r3cUo7NYwwhE+KssYMND42U/z3GABXngzOprRQUCj2CWLbkG4MW5wuSD5cjKWO+YGyJR LoUVcgkTuyG5U8or0lGSAW2IImoYDv3GCo2ifIZJ8eg3jn0q32lIQLGkLq8QRLjQlZy9 iYKKzblYIYDcw2bLx+1FiOTtCAxjVBDgxFC2U9kL/B1TtbwnCW6UzGfXfQ5gGj171Ehn S5CMQrdoL+ZWOxNjlAB6QWMJhjuOVyP2eKo9SXz+9WiPLtAdgUsF6Qz26HW0NZIIxgrA KIKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=tlDkgcE659mvNUmUK6Dqv+T/1aYYlHB/6ptv/S4T04c=; b=o9JVeieV8SiHaCferUnVlSUi7O7yyl2ciCpF/bDGmb8jOq0FsTCZZtFW+pXSYZJ/fG twhuqBcJzMsnh/HlZCT742PfKkwTmZNEr+e/YycMiWxaV/geytnX4cCwUFmGVvkXeLcD 01HdmY1pJU5a8qJo+WNcGLrKr4TMp0IxDOToo/ASd4I/Pzs87hxmAGRly8qXfAK5j04J jyJUvXaHJlworDgyFZ9R98qay1OXAPzsuhh/6Z9Ins+NKwcAlBuw9PN47hLBevP6LLSE 39UMZ5h+3kktNKkV+sL5vAd2v2slcJtEWYlDiiD9ls7IYBHb2KZPSV0ttmE9zta/i55q sPnw== X-Gm-Message-State: AElRT7FoTjxIxt/0IbQqYRbiVHgJYWgonbWSyrVBx4F7p7LoJQbLAnOc HBG1CnP183OL2z9DLnMUdXktUg== X-Google-Smtp-Source: AG47ELvmZj63cQHmyXkc2kIvcH+pdTXmtw5OsAJv4ePj2jF2chc5EQ1o+9rI+atrg6VBoCI8u8SP+g== X-Received: by 10.28.134.5 with SMTP id i5mr2320233wmd.127.1521557948531; Tue, 20 Mar 2018 07:59:08 -0700 (PDT) Received: from bidouze.vm.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id z6sm1050039wre.61.2018.03.20.07.59.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Mar 2018 07:59:07 -0700 (PDT) Date: Tue, 20 Mar 2018 15:58:53 +0100 From: =?iso-8859-1?Q?Ga=EBtan?= Rivet To: Rosen Xu Cc: dev@dpdk.org, declan.doherty@intel.com, bruce.richardson@intel.com, shreyansh.jain@nxp.com, tianfei.zhang@intel.com, hao.wu@intel.com Message-ID: <20180320145853.ypv36jbntafaman4@bidouze.vm.6wind.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Mar 2018 14:59:09 -0000 Hi Rosen, Unless I'm mistaken, this is the v1? Did you mean to send the v2 instead and got mixed up or did I miss something? I would have the same remarks regarding PCI parsing of devices etc. Can you send the v2 as a response to this cover-letter? You have to take the Message-ID of the previous patch and use "--in-reply-to" option from git-send-email. On Tue, Mar 20, 2018 at 09:45:51PM +0800, Rosen Xu wrote: > Intel FPGA BUS in DPDK > ------------------------- > > This patch set introduces Intel FPGA BUS support in DPDK. > > Motivation > ========== > > FPGA is used more and more widely in Cloud and NFV, one primary reason is > that FPGA not only provide ASIC performance but also it's more flexible > than ASIC. FPGA use Partial Reconfigure(PR) Parts of Bitstream to achieve > its flexibility. Another reason is that one FPGA can be shared > by different Users, and each User can use some of AFUs of One FPGA. > > That means One FPGA Device Bitstream is divided into many Parts of > Bitstream(each Part of Bitstream is defined as AFU-Accelerated > Function Unit), and each AFU is a Hardware Acceleration Unit and > it can dynamically Reload respectively. > > Scope > ===== > > The Intel FPGA BUS implementation is target towards various FPGA Devices > use PR to provide many Acceleration Function. Specific PMDs may also > bind to its AFU. And Applications don't care they are using ASIC > Acceleration or FPGA AFU Acceleration. > > Proposed Solution > ================= > - Involve Rawdev to take FPGA Partial Configuration(Download/PR) > - Defined FPGA-BUS for Acceleration Drivers of AFUs > - FPGA PCI Scan(1st Scan) follows DPDK UIO/VFIO PCI Scan Process, > probe Intel FPGA Rawdev Driver > - AFU Scan(2nd Scan) bind DPDK Driver to FPGA Partial-Bitstream > > Status > ===== > With integrating Intel PSG FPGA Software Stack OPAE(Open Programmable > Acceleration Engine) Share Code, Intel FPGA BUS runs well in > Intel PSG FPGA Cards. > > Patch set Information > ==================== > > This patch set includes 6 patches: > * 0 : Introduce the Intel FPGA BUS library and enable its compilation. > * 1 : Adds command parse code, for start-up application > with Intel FPGA BUS. > * 2 : Adds Driver Probe Code, for AFU Drivers should probed > after PCI Drivers. > * 3 : Adds Intel FPGA BUS library code, for AFU Device scan > and AFU Drivers probe. > * 4 : Adds a Intel FPGA rawdevice driver, for FPGA Device Management > such as PR. > * 5 : Adds Intel OPAE(Open Programmable Acceleration Engine) Share Code, > it's Intel FPGA Software Stack. > > Rosen Xu (5): > Add Intel FPGA BUS Command Parse Code > Add Intel FPGA BUS Probe Code > Add Intel FPGA BUS Lib Code > Add Intel FPGA BUS Rawdev Code > Add Intel OPAE Share Code > > drivers/bus/ifpga/Makefile | 64 + > drivers/bus/ifpga/ifpga_bus.c | 573 +++++++ > drivers/bus/ifpga/ifpga_common.c | 154 ++ > drivers/bus/ifpga/ifpga_common.h | 25 + > drivers/bus/ifpga/ifpga_logs.h | 32 + > drivers/bus/ifpga/rte_bus_ifpga.h | 141 ++ > drivers/bus/ifpga/rte_bus_ifpga_version.map | 8 + > drivers/raw/Makefile | 1 + > drivers/raw/ifpga_rawdev/Makefile | 63 + > drivers/raw/ifpga_rawdev/base/Makefile | 54 + > drivers/raw/ifpga_rawdev/base/ifpga_api.c | 543 +++++++ > drivers/raw/ifpga_rawdev/base/ifpga_api.h | 77 + > drivers/raw/ifpga_rawdev/base/ifpga_compat.h | 84 + > drivers/raw/ifpga_rawdev/base/ifpga_defines.h | 1696 ++++++++++++++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c | 861 ++++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h | 38 + > drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c | 340 ++++ > drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h | 197 +++ > drivers/raw/ifpga_rawdev/base/ifpga_fme.c | 763 +++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c | 328 ++++ > drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c | 430 +++++ > drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c | 742 +++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c | 395 +++++ > drivers/raw/ifpga_rawdev/base/ifpga_hw.h | 152 ++ > drivers/raw/ifpga_rawdev/base/ifpga_port.c | 730 +++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_port_error.c | 236 +++ > drivers/raw/ifpga_rawdev/base/opae_debug.c | 126 ++ > drivers/raw/ifpga_rawdev/base/opae_debug.h | 46 + > drivers/raw/ifpga_rawdev/base/opae_hw_api.c | 389 +++++ > drivers/raw/ifpga_rawdev/base/opae_hw_api.h | 276 ++++ > drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c | 151 ++ > drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h | 293 ++++ > drivers/raw/ifpga_rawdev/base/opae_osdep.h | 111 ++ > .../ifpga_rawdev/base/osdep_raw/osdep_generic.h | 104 ++ > .../ifpga_rawdev/base/osdep_rte/osdep_generic.h | 72 + > drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 486 ++++++ > drivers/raw/ifpga_rawdev/ifpga_rawdev.h | 38 + > drivers/raw/ifpga_rawdev/ifpga_rawdev_example.c | 99 ++ > .../ifpga_rawdev/rte_pmd_ifpga_rawdev_version.map | 4 + > lib/librte_eal/common/eal_common_bus.c | 14 +- > lib/librte_eal/common/eal_common_options.c | 8 +- > lib/librte_eal/common/eal_options.h | 2 + > 42 files changed, 10944 insertions(+), 2 deletions(-) > create mode 100644 drivers/bus/ifpga/Makefile > create mode 100644 drivers/bus/ifpga/ifpga_bus.c > create mode 100644 drivers/bus/ifpga/ifpga_common.c > create mode 100644 drivers/bus/ifpga/ifpga_common.h > create mode 100644 drivers/bus/ifpga/ifpga_logs.h > create mode 100644 drivers/bus/ifpga/rte_bus_ifpga.h > create mode 100644 drivers/bus/ifpga/rte_bus_ifpga_version.map > create mode 100644 drivers/raw/ifpga_rawdev/Makefile > create mode 100644 drivers/raw/ifpga_rawdev/base/Makefile > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_compat.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_defines.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_hw.h > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port.c > create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port_error.c > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.c > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.h > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.c > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.h > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h > create mode 100644 drivers/raw/ifpga_rawdev/base/opae_osdep.h > create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_raw/osdep_generic.h > create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_rte/osdep_generic.h > create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.c > create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.h > create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev_example.c > create mode 100644 drivers/raw/ifpga_rawdev/rte_pmd_ifpga_rawdev_version.map > > -- > 1.8.3.1 > -- Gaëtan Rivet 6WIND