From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <bruce.richardson@intel.com> Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id F35392A62 for <dev@dpdk.org>; Wed, 28 Mar 2018 11:37:13 +0200 (CEST) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2018 02:37:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,370,1517904000"; d="scan'208";a="45945290" Received: from bricha3-mobl.ger.corp.intel.com ([10.237.221.52]) by orsmga002.jf.intel.com with SMTP; 28 Mar 2018 02:37:09 -0700 Received: by (sSMTP sendmail emulation); Wed, 28 Mar 2018 10:37:09 +0100 Date: Wed, 28 Mar 2018 10:37:09 +0100 From: Bruce Richardson <bruce.richardson@intel.com> To: Rosen Xu <rosen.xu@intel.com> Cc: dev@dpdk.org, declan.doherty@intel.com, shreyansh.jain@nxp.com, tianfei.zhang@intel.com, hao.wu@intel.com, gaetan.rivet@6wind.com Message-ID: <20180328093708.GA9740@bricha3-MOBL.ger.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522229396-17898-1-git-send-email-rosen.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1522229396-17898-1-git-send-email-rosen.xu@intel.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH v3 0/6] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Wed, 28 Mar 2018 09:37:14 -0000 On Wed, Mar 28, 2018 at 05:29:50PM +0800, Rosen Xu wrote: > Intel FPGA BUS in DPDK > ------------------------- > > This patch set introduces Intel FPGA BUS support in DPDK. > > v3 updates: > =========== > - Remove all modifications of bus scan and probe > - FPGA BUS Scan is trigged by hotplug of Rawdev > - Took Modifications of comments > - Move AFU Device to IFPGA > - FPGA BUS Scan depend on it��s IFPGA Rawdev > - Add Build Macros for FPGA BUS and IFPGA Rawdev > > Questions > ========= > Why not PCI Bus? > All of the AFUs of one FPGA may share same PCI BDF. > Why not vdev Bus? > Because AFUs depend on Rawdev, and it's hardware specpic. > > Motivation > ========== > FPGA is used more and more widely in Cloud and NFV, one primary reason is > that FPGA not only provide ASIC performance but also it's more flexible > than ASIC. FPGA use Partial Reconfigure(PR) Parts of Bitstream to achieve > its flexibility. Another reason is that one FPGA can be shared > by different Users, and each User can use some of AFUs of One FPGA. > > That means One FPGA Device Bitstream is divided into many Parts of > Bitstream(each Part of Bitstream is defined as AFU-Accelerated > Function Unit), and each AFU is a Hardware Acceleration Unit and > it can dynamically Reload respectively. > > Proposed Solution > ================= > - Involve Rawdev to take FPGA Partial Configuration(Download/PR) > - Defined FPGA-BUS for Acceleration Drivers of AFUs > - FPGA PCI Scan(1st Scan) follows DPDK UIO/VFIO PCI Scan Process, > probe Intel FPGA Rawdev Driver. FPGA-BUS scan is called, but AFU > depend on Rawdev, so this scan doesn't trig AFU device create. > - AFU Scan(2nd Scan) bind DPDK Driver to FPGA Partial-Bitstream. > This scan is trigged by hotplug of IFPGA Rawdev probe, in this > scan the AFUs will be created and their dirves are also probed. > > Scope > ===== > The Intel FPGA BUS implementation is target towards various FPGA Devices > use PR to provide many Acceleration Function. Specific PMDs may also > bind to its AFU. And Applications don't care they are using ASIC > Acceleration or FPGA AFU Acceleration. > > > Status > ===== > With integrating Intel PSG FPGA Software Stack OPAE(Open Programmable > Acceleration Engine) Share Code, Intel FPGA BUS runs well in > Intel PSG FPGA Cards. > > > Rosen Xu (6): > Add Intel FPGA BUS Command Parse Code > config/common_base: Add Intel FPGA Build Configuration Macro > mk/rte.app.mk: Add Intel FPGA Bus Build Configuration Macro To App > Script > drivers/bus: Add Intel FPGA Bus Lib Code > drivers/raw/ifpga_rawdev: Add Intel FPGA Rawdev Driver Code > drivers/raw/ifpga_rawdev: Add Intel FPGA OPAE Share Code > > config/common_base | 6 + > drivers/bus/Makefile | 1 + Forgot to mention this on previous versions, but please also include changes to add this to the meson build too. /Bruce