From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-by2nam01on0054.outbound.protection.outlook.com [104.47.34.54]) by dpdk.org (Postfix) with ESMTP id E38C51B801 for ; Tue, 3 Apr 2018 17:37:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=9SZXaRPj34ct2rAbbDA31VgoP3tf2fE8SlY+07qF2zI=; b=od3OCEQILhnr4xaqr6nuV4KRhnJAHdMc/j4Dq6p9Icmx+Gn/YPRhk79Y6FmpxxlJOxt/KHggj7cEogtfbo0NmU60Q4g/oi1IDjO15lLs0dFmukwJ/3uPJn5f2B2L7DFg6SY+Uf/RvEWomw+qMFglsy0rxIxPAtiJilSSe++KZeA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.JacobKollanukkaran@cavium.com; Received: from jerin (106.201.49.151) by BN3PR07MB2513.namprd07.prod.outlook.com (2a01:111:e400:7bbf::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.653.12; Tue, 3 Apr 2018 15:37:23 +0000 Date: Tue, 3 Apr 2018 21:07:04 +0530 From: Jerin Jacob To: Olivier Matz Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com Message-ID: <20180403153703.GA19072@jerin> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> MIME-Version: 1.0 Content-Type: text/plain; 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The > > > size of rte_ring structure and the offset of the fields remain > > > the same on platforms with cache line size = 64B: > > > > > > rte_ring = 384 > > > rte_ring.name = 0 > > > rte_ring.flags = 32 > > > rte_ring.memzone = 40 > > > rte_ring.size = 48 > > > rte_ring.mask = 52 > > > rte_ring.prod = 128 > > > rte_ring.cons = 256 > > > > > > But it has an impact on platform where cache line size is 128B: > > > > > > rte_ring = 384 -> 768 > > > rte_ring.name = 0 > > > rte_ring.flags = 32 > > > rte_ring.memzone = 40 > > > rte_ring.size = 48 > > > rte_ring.mask = 52 > > > rte_ring.prod = 128 -> 256 > > > rte_ring.cons = 256 -> 512 > > > > Are we leaving TWO cacheline to make sure, HW prefetch don't load > > the adjust cacheline(consumer)? > > > > If so, Will it have impact on those machine where it is 128B Cache line > > and the HW prefetcher is not loading the next caching explicitly. Right? > > The impact on machines that have a 128B cache line is that an unused > cache line will be added between the producer and consumer data. I > expect that the impact is positive in case there is a hw prefetcher, and > null in case there is no such prefetcher. It is not NULL, Right? You are loosing 256B for each ring. > > On machines with 64B cache line, this was already the case. It just > reduces the alignment constraint. Not all the 64B CL machines will have HW prefetch. I would recommend to add conditional compilation flags to express HW prefetch enabled or not? based on that we can decide to reserve the additional space. By default, in common config, HW prefetch can be enabled so that it works for almost all cases. > > Olivier