From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-DM3-obe.outbound.protection.outlook.com (mail-dm3nam03on0075.outbound.protection.outlook.com [104.47.41.75]) by dpdk.org (Postfix) with ESMTP id C4B381C68D for ; Thu, 5 Apr 2018 10:02:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=nBdNW/7aPIixTS7mW25i4FdkRdtUCVKwpglJT7Jt6ts=; b=A8kL0YkrbbIPn85Rj/N6eXz94yqMrE98r7F3Ot0RlB9pF+goNCezKSo+cnsYCz0LZ0I9PwsSwLr2vyTuXoqGDxsbIDqb7Q2i5BBTJWW6fqHLhAJRyCjJvKgl1wnrgpkWA+w9oB9bM8AzHZIqRInq5I+XpL5AUgBimIFixMbEdVk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.JacobKollanukkaran@cavium.com; Received: from jerin (111.93.218.67) by SN2PR07MB2526.namprd07.prod.outlook.com (2603:10b6:804:6::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.631.10; Thu, 5 Apr 2018 08:01:57 +0000 Date: Thu, 5 Apr 2018 13:31:35 +0530 From: Jerin Jacob To: "Ananyev, Konstantin" Cc: Olivier Matz , "dev@dpdk.org" , "Richardson, Bruce" Message-ID: <20180405080134.GA2674@jerin> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> <20180403155601.rqb7fhu6vggzrh7e@platinum> <20180403163254.GB19072@jerin> <2601191342CEEE43887BDE71AB977258A0AB90E3@irsmsx105.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; 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Ananyev, Konstantin ; Richardson, Bruce > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure > > > > -----Original Message----- > > > Date: Tue, 3 Apr 2018 17:56:01 +0200 > > > From: Olivier Matz > > > To: Jerin Jacob > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring > > > structure > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > On Tue, Apr 03, 2018 at 09:07:04PM +0530, Jerin Jacob wrote: > > > > -----Original Message----- > > > > > Date: Tue, 3 Apr 2018 17:25:17 +0200 > > > > > From: Olivier Matz > > > > > To: Jerin Jacob > > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring > > > > > structure > > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > > > On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote: > > > > > > -----Original Message----- > > > > > > > Date: Tue, 3 Apr 2018 15:26:44 +0200 > > > > > > > From: Olivier Matz > > > > > > > To: dev@dpdk.org > > > > > > > Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring > > > > > > > structure > > > > > > > X-Mailer: git-send-email 2.11.0 > > > > > > > > > > > > > > The initial objective of > > > > > > > commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") > > > > > > > was to add an empty cache line betwee, the producer and consumer > > > > > > > data (on platform with cache line size = 64B), preventing from > > > > > > > having them on adjacent cache lines. > > > > > > > > > > > > > > Following discussion on the mailing list, it appears that this > > > > > > > also imposes an alignment constraint that is not required. > > > > > > > > > > > > > > This patch removes the extra alignment constraint and adds the > > > > > > > empty cache lines using padding fields in the structure. The > > > > > > > size of rte_ring structure and the offset of the fields remain > > > > > > > the same on platforms with cache line size = 64B: > > > > > > > > > > > > > > rte_ring = 384 > > > > > > > rte_ring.name = 0 > > > > > > > rte_ring.flags = 32 > > > > > > > rte_ring.memzone = 40 > > > > > > > rte_ring.size = 48 > > > > > > > rte_ring.mask = 52 > > > > > > > rte_ring.prod = 128 > > > > > > > rte_ring.cons = 256 > > > > > > > > > > > > > > But it has an impact on platform where cache line size is 128B: > > > > > > > > > > > > > > rte_ring = 384 -> 768 > > > > > > > rte_ring.name = 0 > > > > > > > rte_ring.flags = 32 > > > > > > > rte_ring.memzone = 40 > > > > > > > rte_ring.size = 48 > > > > > > > rte_ring.mask = 52 > > > > > > > rte_ring.prod = 128 -> 256 > > > > > > > rte_ring.cons = 256 -> 512 > > > > > > > > > > > > Are we leaving TWO cacheline to make sure, HW prefetch don't load > > > > > > the adjust cacheline(consumer)? > > > > > > > > > > > > If so, Will it have impact on those machine where it is 128B Cache line > > > > > > and the HW prefetcher is not loading the next caching explicitly. Right? > > > > > > > > > > The impact on machines that have a 128B cache line is that an unused > > > > > cache line will be added between the producer and consumer data. I > > > > > expect that the impact is positive in case there is a hw prefetcher, and > > > > > null in case there is no such prefetcher. > > > > > > > > It is not NULL, Right? You are loosing 256B for each ring. > > > > > > Is it really that important? > > > > Pipeline or eventdev SW cases there could more rings in the system. > > I don't see any downside of having config option which is enabled > > default. > > > > In my view, such config options are good, as in embedded usecases, customers > > can really fine tune the target for the need. In server usecases, let the default > > of option be enabled, no harm. > > But that would mean we have to maintain two layouts for the rte_ring structure. Is there any downside of having two configurable layout? meaning, we are not transferring rte_ring structure over network etc(ie no interoperability issue). Does it really matter? May I am missing something here. I was thinking like this: in config/common_base: CONFIG_RTE_EAL_HAS_HW_PREFETCH=y #ifdef RTE_EAL_HAS_HW_PREFETCH #define EMPTY_CACHE_LINE char pad0 __rte_cache_aligned #else #define EMPTY_CACHE_LINE #endif struct rte_ring_headtail { .. .. char pad0 __rte_cache_aligned; /**< empty cache line */ struct rte_ring_headtail prod __rte_cache_aligned; EMPTY_CACHE_LINE struct rte_ring_headtail cons __rte_cache_aligned; EMPTY_CACHE_LINE }