From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by dpdk.org (Postfix) with ESMTP id 04F601B54E for ; Wed, 11 Jul 2018 22:49:20 +0200 (CEST) Received: by mail-pf0-f193.google.com with SMTP id s21-v6so19173934pfm.6 for ; Wed, 11 Jul 2018 13:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uONuzQ3Kz/Fm1HxT9Nwvn4YNEqdM8EWX4f+FFLIC/fs=; b=S8sEInLZ5MvjSjcD0Prv0GOKLzMhihokEo1N3fgQyIBjZ+cC5IU9BSGiSuZypDZaEe NhPR9pwTZjM6F/lOvWGlNpaVIAHciDe52qdzPPdx67og3Co+gMXbM5UaAeI5TZsTqZrQ lB4Et1OH024WfvDzAqEyr7PzuS4u4HthhMJLJloZmL0HoyIs06tl/CLkdPogwTATr2es yRWlvwPrmYAkewWBd2ucQPfHl5RVz0vBJ9xZqbn39FFqBp5ru39f+g9MFZkynXs9YsxQ /iN7OOVKDzBSTV4D8vL34DkWd/0FTdSfYXA82vXQneC9Ct0rwSK2VWtR8nHaYOEPpRRU OdHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uONuzQ3Kz/Fm1HxT9Nwvn4YNEqdM8EWX4f+FFLIC/fs=; b=uoWwy070LWaKWbuBAV1baa0CTN50Ph1UMbCGkApurmr+PPx7Hi9dt2vSo3tuW2kGra u2Iy4lrbxmH9GZLFcXzO5BQgGnISafXaubAbcjfTe0qnHWlyoSQkhO9HWYB3fSUpuDi8 pa9L/83IfEiIMVmcX09BF+znFFFnfZP3EAtqkwBgfASBU6Geh9ciWGVtYQucvxKs6Ffg 3+xB1GFjPuQdesOwrdPuaNlBlgikXFzLuVmh47RuG2cng72WM/S3xJK2g3c2ETtONlQd nkKLHeHzyXv1O7K4y8Ctchvdt120F29Jvet7T5k7asoXP9wojjhhvz6DpioVtSiMEDoF pfiA== X-Gm-Message-State: AOUpUlF+UyWKmp/p+p69ajqKrRa65tflAM9ZL+NDUYVFfszofnG3ueO4 k/WWz4dGXK/KtSJUxbibLC/HSw== X-Google-Smtp-Source: AAOMgpcwPK956mpMdv8q2SBhIc18xI68k3CqZTRetvewJdSSEe+KZHF2Qf4qRF588UGnvNfeUA1IzQ== X-Received: by 2002:a63:1722:: with SMTP id x34-v6mr174219pgl.268.1531342157880; Wed, 11 Jul 2018 13:49:17 -0700 (PDT) Received: from xeon-e3 (204-195-22-127.wavecable.com. [204.195.22.127]) by smtp.gmail.com with ESMTPSA id d17-v6sm28465829pgp.50.2018.07.11.13.49.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Jul 2018 13:49:17 -0700 (PDT) Date: Wed, 11 Jul 2018 13:49:07 -0700 From: Stephen Hemminger To: Yipeng Wang Cc: pablo.de.lara.guarch@intel.com, dev@dpdk.org, bruce.richardson@intel.com, honnappa.nagarahalli@arm.com, vguvva@caviumnetworks.com, brijesh.s.singh@gmail.com Message-ID: <20180711134907.01d8eaf0@xeon-e3> In-Reply-To: <1531242001-381104-6-git-send-email-yipeng1.wang@intel.com> References: <1528455078-328182-1-git-send-email-yipeng1.wang@intel.com> <1531242001-381104-1-git-send-email-yipeng1.wang@intel.com> <1531242001-381104-6-git-send-email-yipeng1.wang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v5 5/8] hash: add read and write concurrency support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jul 2018 20:49:20 -0000 On Tue, 10 Jul 2018 09:59:58 -0700 Yipeng Wang wrote: > + > +static inline void > +__hash_rw_reader_lock(const struct rte_hash *h) > +{ > + if (h->readwrite_concur_support && h->hw_trans_mem_support) > + rte_rwlock_read_lock_tm(h->readwrite_lock); > + else if (h->readwrite_concur_support) > + rte_rwlock_read_lock(h->readwrite_lock); > +} > + > +static inline void > +__hash_rw_writer_unlock(const struct rte_hash *h) > +{ > + if (h->multi_writer_support && h->hw_trans_mem_support) > + rte_rwlock_write_unlock_tm(h->readwrite_lock); > + else if (h->multi_writer_support) > + rte_rwlock_write_unlock(h->readwrite_lock); > +} > + > +static inline void > +__hash_rw_reader_unlock(const struct rte_hash *h) > +{ > + if (h->readwrite_concur_support && h->hw_trans_mem_support) > + rte_rwlock_read_unlock_tm(h->readwrite_lock); > + else if (h->readwrite_concur_support) > + rte_rwlock_read_unlock(h->readwrite_lock); > +} > + For small windows, reader-writer locks are slower than a spin lock because there are more cache bounces.